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STV3550

7.7.9

Transmit & Receive Buffers

The transmit and receive buffers are used to allow the SSC2 to do back-to-back transfers (i.e.

continuous clock and data transmission).

The transmit buffer (SSCTBUF), is written with the data to be sent out of the SSC2. This is loaded

into the shift register for transmission. Once this has been done, the SSCTBUF is then available to

be loaded again with a new data frame. This is indicated by the assertion of the transmit interrupt

request status bit, SSCTIR, which indicates that the transmit buffer is empty. This will cause an

interrupt if the transmit buffer empty interrupt is enabled by setting the SSCTIEN bit in the interrupt

enable register.

A transmission is started in master mode by a write to the transmit buffer. This starts the clock

generation circuit and loads the shift register with the new data.

Continuous transfers of data are therefore possible, by reloading the transmit buffer whenever the

interrupt is received. The software interrupt routine has the length of time for a complete data frame

in order to refill the buffer, before it is next emptied. If the transmit buffer is not reloaded in time,

when in slave mode, a transmit error condition, SSCTE (see Section 7.7.13: Error Detection) is

generated.

The number of bits to be loaded into the transmit buffer is determined by the frame data width

selected in the control register, SSCBM. The unused bits are ignored.

The receive buffer (SSCRBUF) is loaded from the shift register when a complete data frame has

been shifted in. This is indicated by the assertion of the receive interrupt request status bit,

SSCRIR, which indicates that the receive buffer is full. This will cause an interrupt if the receive

buffer full interrupt is enabled by setting the SSCRIEN in the interrupt enable register.

The CPU should then read out the contents of this register before the next data frame has been

received otherwise the buffer will be reloaded from the shift register over the top of the previous

data. This will be indicated as a receive error condition, SSCRE, (see Section 7.7.13: Error

Detection).

The number of bits which will be loaded into the receive buffer is determined by the frame data width

selected in the control register, SSCBM. The unused bits are not valid and should be ignored.

7.7.10 Loopback Mode

A loopback mode is provided which connects the serial_data_out to serial_data_in. This allows

software and testing to be done without the need for an external bus device. This mode is enabled

by setting the SSCLPB bit in the control register. A setting of logic 1 enables loopback, logic 0 puts

the SSC2 into normal operation.

7.7.11 Enabling Operation

The transmission and reception of data by the SSC2 block can be enabled or disabled by setting

the SSCEN bit in the control register. A setting of logic 1 turns on the SSC2 block for transmission

and reception. Logic 0 prevents the block from reading or writing data to the serial_data in and out

ports.

7.7.12 Master/Slave Operation

A number of features of the SSC2 are controlled by whether the block is in master or slave mode.

For example, in master mode the SSC2 will generate the serial_clock signal according to the setting

of baud rate, polarity and phase. In slave mode, no clock is generated and instead the assumption

is that an external device is generating the serial_clock.

Master or slave mode is set by the SSCMS bit in the control register. A setting of logic 0 means the

SSC2 is in slave mode, a setting of logic 1 puts the device into master mode.

STV3550 Datasheet(PDF) 104 Page - STMicroelectronics

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