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STV3550 Datasheet(PDF) 107 Page - STMicroelectronics |
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STV3550 Datasheet(HTML) 107 Page - STMicroelectronics |
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107 / 144 page  STV3550 107/144 7.7.16 I²C Operation This section describes the hardware features which are implemented in order to allow full support for the I²C bus standard. The architecture of the I²C including all the I²C hardware additions is shown in Figure 69. 7.7.16.1 I²C Control There are a number of features of the I²C-bus protocol which require special control: 1. To allow slow slave devices to be accessed, and to allow multiple master devices to generate a consistent clock signal, a clock synchronization mechanism is specified. 2. START and STOP conditions must be recognized when in slave mode or multi-master mode. A START condition initiates the address comparison phase. A STOP condition indicates that a master has completed transmission and that the bus is now free. Figure 69: SSC2 Architecture with I²C Hardware Clock Generator Clock Stretcher START/STOP Detect Shift Register Arbitration Checker Acknowledge Generator Transmit Buffer Receive Buffer Peripheral Interface serial_clock_in serial_data_in serial_data_out serial_clock_out START/STOP Generator I²C Control Slave Address Comparison |
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