STV3550 datasheet(111/144 Pages) STMICROELECTRONICS

111 / 144 page

STV3550

111/144

7.7.19 START/STOP Condition Detection

START/STOP conditions are only generated by a master device. A slave device must detect the

START condition and expect the next byte (or 2 bytes in 10 bit addressing) to be a slave address. A

STOP condition is used to detect when the bus is free.

A START condition is when the transmit/receive data line goes from high to low DURING the high

period of the clock line. It indicates that a master device wants control of the bus. In a single master

configuration, it will automatically get control, in a multi-master configuration, it begins to transmit as

part of the arbitration procedure, and may or may not get control (see Section 7.7.24: Arbitration

Checking).

A STOP condition is when the transmit/receive data line goes from low to high DURING the high

period of the clock line. It indicates that a master device has relinquished control of the bus (the bus

will be free a specified time after the stop condition).

An additional piece of hardware is provided on the SSC2 to detect START and STOP conditions.

This is necessary in slave mode because it cannot be done in time by programming the PIO pads.

There is not sufficient time for a software interrupt between the end of the START condition and the

beginning of the data transmitted by a remote master.

START and STOP conditions are detected by sampling the data line continuously when the clock

line is high. The same edge detection mechanism as for the serial clock is used to determine if the

data line changes. If a falling edge is seen then a START condition is detected. If a rising edge is

seen then a STOP condition is detected. The sampling approach allows an element of spike

suppression on the data line.

The START and STOP condition detection is enabled when the I²C control bit, SSCI2CM, is set in

the I²C control register.

When a START condition is triggered, the SSC2 will inform the I²C control block which will then

initiate the address comparison phase.

When a STOP condition is triggered the SSC2 will set the SSCSTOP bit in the status register. It will

also generate an interrupt if the SSCSTOPEN bit is set in the interrupt enable register.

The interrupt and the status bit will be cleared when the status register is read.

7.7.20 Slave Address Comparison

After a START condition has been detected, the SSC2 goes into the address comparison phase.

It receives the first 8 bits of the next byte transmitted and compares the first 7 bits against the

address stored in the slave address register, SSCSLAD. If they match, then the address

comparison block indicates this to the I²C control block.

This will then generate an acknowledge bit in the next bit position and will set the addressed as

slave bit, SSCAAS, in the status register. An interrupt will then be generated after the acknowledge

bit if the addressed as slave enable bit, SSCAASEN, it set in the interrupt enables register. This

interrupt and status bit will be cleared by a write to the transmit buffer.

The 8th bit of the first byte indicates whether the SSC2 will be written to (LOW) or read from (HIGH).

This will be used by the control block to determine if it needs to acknowledge the following data

bytes (i.e. when receiving data).

When 10 bit addressing mode is selected by setting the 10 bit addressing bit, SSCAD10, the first 7

bits of the first data byte will be compared against “11110XX”, where XX are the 2 most significant

bits of the 10 bit address stored in the slave address register.

The read/write bit then determines what to do next.

STV3550 Datasheet(PDF) 111 Page - STMicroelectronics

STV3550 Datasheet(HTML) 111 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL