STV3550 datasheet(113/144 Pages) STMICROELECTRONICS

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STV3550

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Between STOP and START conditions the bus is free and the clock and data lines must be held

high. The I²C control block determines this holds the lines high between transactions.

The START/STOP generator is controlled by the START condition generate bit, SSCSTRTG and

the STOP condition generate bit, SSCSTOPG in the I²C control register.

The generator will pull the serial_data_out line LOW during the high period of the clock to produce

a START condition. In the case of a STOP condition it will pull the data line HIGH.

However, a START condition will only be generated if the bus is currently free (i.e. the SSCBUSY bit

in the status register is LOW). This is to prevent the SSC2 from generating a START condition when

another master has just generated one.

If a START condition cannot be generated because the bus is busy, then the generator will force the

arbitration checker to generate an arbitration lost interrupt and prevent data from being transmitted

for the next byte. The software interrupt handler is therefore informed of the aborted transmission

when servicing the interrupt.

To properly generate the timing waveforms of the START and STOP conditions, the SSC2 contains

a timing counter. This ensures the minimum setup and hold times are met with some additional

margin.

7.7.23 Acknowledge Bit Generation

For I²C operation, it is required to both detect acknowledge bits when transmitting data, and

generate them when receiving data.

An acknowledge bit must be transmitted by the receiver at the end of every 8 bit data frame. The

transmitter must verify that an acknowledge bit has been received before continuing.

An acknowledge bit will not be generated by a master receiver for the last byte it wishes to receive.

This “not acknowledge” is used by the slave device to determine when to stop transmission.

The acknowledge bit is generated by the receiver after the 8 data bits have been transferred to it. In

the 9th clock pulse, the transmitter holds the data line high and the receiver must pull the line low to

acknowledge receipt. If the receiver is unable to acknowledge receipt, then the master will generate

a stop condition to abort the transfer.

Acknowledge bits are generated by the SSC2 when the acknowledge generation bit, SSCACKG, is

set in the I²C control register. They are only generated when receiving data.

When in master mode and receiving data the SSCACKG bit should be set to 0 before the last byte

to be received.

The SSC2 will automatically generate acknowledge bits when addressed as a slave device.

7.7.24 Arbitration Checking

This situation only arises when two or more master devices generate a START condition within the

minimum hold time of the bus standard. This generates a valid start condition on the bus with more

than one master valid. However, a master device cannot determine if two or more masters have

generated a START condition, so arbitration is always enabled.

The arbitration for who wins control of the bus is determined by which master is the first to transmit

a low data bit on the data line when the other master wants to send a high bit. This master wins

control of the bus.

Therefore a master which detects a different data bit on its input to that which it transmitted must

switch off its output stage for the rest of the 8 bit data byte, as it has lost the arbitration.

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