STV3550 datasheet(116/144 Pages) STMICROELECTRONICS

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STV3550

7.8

Asynchronous Serial Controller (ASC)

The Asynchronous Serial Controller, also referred to as the UART interface, provides serial

communication between the STV3550 and other microcontrollers, microprocessors or external

peripherals.

Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable.

Parity, framing, and overrun error detection is provided to increase the reliability of data transfers.

Transmission and reception of data can simply be double-buffered, or 16-deep FIFOs may be used.

Handshaking is supported on both transmission and reception. For multiprocessor communication,

a mechanism to distinguish the address from the data bytes is included. Testing is supported by a

loop-back option. A dual mode 16-bit baud rate generator provides the ASC with a separate serial

clock signal.

The ASC supports full-duplex asynchronous communication, where both the transmitter and the

receiver use the same data frame format and the same baud rate. Data is transmitted on the

transmit data output pin TxD and received on the receive data input pin RxD.

The registers for the ASC are grouped in a 4 Kbyte block, with the base of the block for ASC

number n at the address ASCnBaseAddress. The value of each ASCnBaseAddress is given in the

7.8.1

Control

The ASC_n_control register controls the operating mode of the ASC. It contains control and

enable bits, error check selection bits, and status flags for error identification.

Serial data transmission or reception is only possible when the baud rate generator run bit (Run) is

set to 1. When the Run bit is set to 0, TxD will be 1. Setting the Run bit to 0 will immediately freeze

the state of the transmitter and receiver and should only be done when the ASC is idle.

Note: Programming the mode control field (Mode) to one of the reserved combinations may result

in unpredictable behavior.

The ASC can be set to use either double-buffering or a 16-deep FIFO on transmission and

reception.

7.8.1.1 Resetting the FIFOs

The ‘registers’ ASC_n_TxReset and ASC_n_RxReset have no actual storage associated with

them. A write of any value to one of these registers resets the corresponding FIFO.

7.8.1.2 Transmission and Reception

Serial data transmission or reception is only possible when the baud rate generator run bit (Run) is

set to 1. A handshaking protocol is supported on both transmission and reception, using CTS and

RTS signals.

A transmission is started by writing to the transmit buffer register ASC_n_TxBuffer. Because data

transmission is double-buffered or uses a FIFO (selectable in the ASC_n_Control register), a new

character may be written to the transmit buffer register before the transmission of the previous

character is complete. This allows characters to be sent back-to-back without gaps.

Data reception is enabled by the receiver enable bit (RxEnable) in the control register. After

reception of a character has been completed, the received data and, if provided by the selected

operating mode, the parity error bit, can be read from the receive buffer register ASC_n_RxBuffer.

Reception of a second character may begin before the received character has been read out of the

receive buffer register. The overrun error status flag (OverrunError) in the status register

ASC_n_Status will be set when the receive buffer register has not been read by the time reception

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