STV3550 datasheet(112/144 Pages) STMICROELECTRONICS

112 / 144 page

112/144

STV3550

If the read/write bit is LOW, indicating a write, then an acknowledge must be generated for the byte,

but the addressed as slave status bit and interrupt are not yet asserted. Instead, the address

comparator will wait for the next data byte and will compare this against the 8 least significant bits of

the slave address register.

If this also matches, then the SSC2 is being addressed, so the second byte is acknowledged and

the addressed as slave bit is set. An interrupt also occurs after the acknowledge bit if the addressed

as slave interrupt enable is set.

On the other hand if the first byte sent had the read/write bit HIGH, then the SSC2 should only

acknowledge if it has previously been addressed and a STOP condition has not yet occurred (i.e.

the master has generated a repeated START condition). In this case the addressed as slave bit is

set here, after the first byte plus acknowledge and an interrupt is generated if the interrupt enable is

set. The second byte in this case will be sent by the SSC2 as this is a read operation.

In all cases if the address does not match, then the SSC2 ignores further data until a STOP

condition is detected.

7.7.21 Clock Stretching

The I²C standard allows slave devices to hold the clock line low if they need more time to process

the data being received (see Section 7.7.18: Clock Synchronization). The SSC2 takes advantage of

this by inserting extended clock low periods. This is done to allow a software device driver to

process the interrupt conditions when in slave mode.

The clock stretching mechanism is used in the following situations:-

1. When the SSC2 has been addressed as a slave device and the interrupt has been enabled.

The clock stretch occurs immediately after the first byte with acknowledge, after a START

condition has occurred (or in the case of 10 bit addressing this might occur after the second

byte plus acknowledge). This gives the software interrupt routine time to initialize for

transmission or reception of data.

2. When the SSC2 is in slave mode and is transmitting or receiving. The clock stretch occurs

immediately after each data byte plus acknowledge. When transmitting, this allows the

software interrupt routine to check that the master has acknowledged before writing the next

data byte into the transmit buffer. If no acknowledge is received, then the software must stop

transmitting bytes. When receiving it allows the software to read the next data byte before the

master starts to send the next one.

3. When the SSC2 loses arbitration. The clock stretch occurs immediately after the current data

byte and acknowledge have been performed. This gives the software time to abort its current

transmission and prepare to retry after the next STOP condition.

Clock stretching is always cleared by a write to the transmit buffer. However, the clock stretch is

only cleared after the required data setup time has expired, otherwise the new transmit buffer data

may affect the value on the data line close to the clock edge.

If a clock stretching event occurs but no relevant interrupt is enabled then the clock will be stretched

indefinitely until the next transmit buffer write. Hence it is important that the correct interrupts are

always enabled. There is a clock stretch status bit, SSCCLST, which indicates when clock

stretching is in operation. This will be cleared after the data setup time after the transmit buffer is

written to.

7.7.22 START/STOP Condition Generation

As a master device the SSC2 must generate a START condition before transmission of the first byte

can start. It may also generate repeated START conditions. It must complete its access to the bus

with a STOP condition.

STV3550 Datasheet(PDF) 112 Page - STMicroelectronics

STV3550 Datasheet(HTML) 112 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL