STV3550 datasheet(109/144 Pages) STMICROELECTRONICS

109 / 144 page

STV3550

109/144

To perform 10 bit address comparison and address acknowledge generation, the 10 bit addressing

mode bit, SSCAD10 must be set (see Section 7.7.20: Slave Address Comparison).

The clock stretching mechanism is enabled for various interrupt conditions when the I²C control

enable bit, SSCI2CM is set (see Section 7.7.21: Clock Stretching).

To generate a START condition, the I²C START condition generate bit, SSCSTRTG, must be set

(see Section 7.7.22: START/STOP Condition Generation).

To generate a STOP condition, the I²C STOP condition generate bit, SSCSTOPG, must be set (see

Section 7.7.22: START/STOP Condition Generation).

To generate acknowledge bits (i.e. a LOW data bit), after each 8 bit data byte when receiving data,

the acknowledge generation bit, SSCACKG, must be set. When receiving data as a master, this bit

must be reset to 0 before the final data byte is received, thereby signalling to the slave to stop

transmitting (see Section 7.7.23: Acknowledge Bit Generation).

To indicate to the software that various situations have arisen on the I²C-bus, a number of status bits

are provided in the status register, SSCSTAT. In addition, some of these bits can generate interrupts

if corresponding bits are set in the interrupt enable register, SSCIEN.

To indicate that the SSC2 has been accessed as a slave device, the addressed as slave bit,

SSCAAS, is set. This will also cause an interrupt if the SSCAASEN bit is set in the interrupt enable

The interrupt will occur after the SSC2 has generated the address acknowledge bit. In 10 bit

addressing mode, the interrupt will occur after the second byte acknowledge bit, in the situations

where 2 bytes of address are sent, or it will occur after the first byte acknowledge in the situation

where only one byte is required.

Until the status bit is reset, the SSC2 will hold the clock line LOW (see Section 7.7.21: Clock

Stretching). This forces the master device to wait until the software has processed the interrupt.

The status bit and the interrupt are reset by writing to the transmit buffer, SSCTBUF.

To indicate that a STOP condition has been received the STOP condition detected bit, SSCSTOP is

set. This will also cause an interrupt if the SSCSTOPEN bit is set in the interrupt enable register.

The SSCSTOP interrupt and status bit will be reset by a read of the status register, SSCSTAT.

To indicate that the SSC2 has lost the arbitration process, when in a multi-master configuration, the

arbitration lost bit, SSCARBL, is set. This will also result in an interrupt if the SSCARBLEN bit is set

in the interrupt enable register. The interrupt will occur immediately after the arbitration is lost.

Until the status bit is reset, the SSC2 will hold the clock line LOW at the end of the current data

frame, (see Section 7.7.21: Clock Stretching). This forces the winning master device to wait until the

software has processed the interrupt.

The interrupt and status bit will be reset by a read of the status register, SSCSTAT.

To indicate that the I²C-bus is busy (i.e. between a START and a STOP condition), the I²C bus busy

bit, SSCBUSY, is set. This does not generate an interrupt.

7.7.17 Clock Period In I²C Mode

The I²C standard requires that at 400KBits/s the clock low period is longer than the clock high

period. This is performed by adding a constant (based in the system clock frequency) to the clock

low period count and subtracting the count from the clock high period count. This mechanism is

enabled for all frequencies when the SSCI2CM bit is set.

STV3550 Datasheet(PDF) 109 Page - STMicroelectronics

STV3550 Datasheet(HTML) 109 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL