CS5530A datasheet(46/259 Pages) NSC

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Revision 1.1

Functional Description (Continued)

3.2

PCI BUS INTERFACE

The PCI bus interface is compliant with the PCI Bus Speci-

fication Rev. 2.1.

The CS5530A acts as a PCI target for PCI cycles initiated

by the processor or other PCI master devices, or as an initi-

ator for DMA, ISA, IDE, and audio master transfer cycles. It

supports positive decode for memory and I/O regions and

is the subtractive decode agent on the PCI bus. The

CS5530A also generates address and data parity and per-

forms parity checking. A PCI bus arbiter is not part of the

CS5530A; however, one is included in the GX-series pro-

cessor.

The PCI Command Register, located at F0 Index 04h

(Table 3-2), provides the basic control over the CS5530A’s

ability to respond and perform PCI bus accesses.

3.2.1

PCI Initiator

The CS5530A acts as a PCI bus master on behalf of the

DMA controller or ISA, IDE, and audio interfaces. The

REQ# and GNT# signals are used to arbitrate for the PCI

bus.

Note:

In a GX-series processor based system, the

REQ#/GNT# signals of the CS5530A must con-

nect to the REQ0#/GNT0# of the processor. This

configuration ensures that the CS5530A is treated

as a non-preemptable PCI master by the proces-

sor.

TheCS5530A asserts REQ#inresponsetoabus master-

ing or DMA request for ownership of the PCI bus. GNT# is

asserted by the PCI arbiter (i.e., processor) to indicate that

access to the PCI bus has been granted to the CS5530A.

The CS5530A then issues a grant to the DMA controller.

This mechanism prevents any deadlock situations across

the bridge. Once granted the PCI bus, the ISA master or

DMA transfer commences.

If an ISA master executes an I/O access, that cycle

remains on the ISA bus and is not forwarded to the PCI

bus. The CS5530A performs only single transfers on the

PCI bus for legacy DMA cycles.

Table 3-2. PCI Command Register

Bit

Description

F0 Index 04h-05h

PCI Command Register (R/W)

Reset Value = 000Fh

15:10

Reserved: Set to 0.

Fast Back-to-Back Enable (Read Only): This function is not supported when the CS5530A is a master. It is always

disabled (always reads 0).

SERR#: Allow SERR# assertion on detection of special errors. 0 = Disable (Default);1 =Enable.

Wait Cycle Control (Read Only): This function is not supported in the CS5530A. It is always disabled

(always reads 0).

Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when

a parity error is detected. 0 = Disable (Default); 1 = Enable.

VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A. It is always disabled (always

reads 0).

Memory Write and Invalidate: Allow the CS5530A to do memory write and invalidate cycles, if the PCI Cache Line Size

Special Cycles: Allow the CS5530A to respond to special cycles. 0 = Disable; 1 = Enable (Default).

This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle.

Bus Master: Allow the CS5530A bus mastering capabilities. 0 = Disable; 1 = Enable (Default).

This bit must be set to 1.

Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

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