CS5530A datasheet(100/259 Pages) NSC

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Functional Description (Continued)

PIC Shadow Register

The PIC registers are shadowed to allow for Save-to-

Disk/RAM to save/restore the PIC state by reading the

PIC’s write-only registers. A write to this register resets the

read sequence to the first register. The read sequence for

the shadow register is listed in F0 Index B9h (Table 3-45).

Table 3-45. PIC Shadow Register

Bit

Description

F0 Index B9h

PIC Shadow Register (RO)

Reset Value = xxh

7:0

PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Con-

troller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it.

A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last

data written to that location.

The read sequence for this register is:

1. PIC1 ICW1

2. PIC1 ICW2

3. PIC1 ICW3

4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0

5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

7. PIC2 ICW1

8. PIC2 ICW2

9. PIC2 ICW3

10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0

11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register value,

then with the shadow register value ORed with C0h.

CS5530A Datasheet(PDF) 100 Page - National Semiconductor (TI)