PC7447 datasheet(7/66 Pages) ATMEL

7 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

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MESI data cache coherency maintained in hardware

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Separate copy of data cache tags for efficient snooping

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Parity support on cache and tags

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No snooping of instruction cache except for icbi instruction

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Data cache supports AltiVec LRU and transient instructions

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Critical double- and/or quad-word forwarding is performed as needed.

Critical quad-word forwarding is used for AltiVec loads and instruction

fetches. Other accesses use critical double-word forwarding

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Level 2 (L2) cache interface

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On-chip, 512 Kbyte, eight-way set-associative unified instruction and data

cache

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Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

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A total nine-cycle load latency for an L1 data cache miss that hits in L2

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PLRU replacement algorithm

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Cache write-back or write-through operation programmable on a per-page or

per-block basis

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64-byte, two-sectored line size

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Parity support on cache

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Level 3 (L3) cache interface (not implemented on PC7447)

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Provides critical double-word forwarding to the requesting unit

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Internal L3 cache controller and tags

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External data SRAMs

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Support for 1, 2, and 4M bytes (MB) total SRAM space

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Support for 1 or 2 MB of cache space

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Cache write-back or write-through operation programmable on a per-page or

per-block basis

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64-byte (1 MB) or 128-byte (2 MB) sectored line size

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Private memory capability for half (1 MB minimum) or all of the L3 SRAM

space for a total of 1-, 2-, or 4-MB of private memory

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Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2

pipelined synchronous Burst SRAMs, and pipelined (register-register) Late

Write synchronous Burst SRAMs

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Supports parity on cache and tags

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Configurable core-to-L3 frequency divisors

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64-bit external L3 data bus sustains 64-bit per L3 clock cycle

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Separate memory management units (MMUs) for Instructions and data

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52-bit virtual address; 32- or 36-bit physical address

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Address

translation

for

4 Kbyte pages, variable-sized blocks, and

256M bytes segments

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Memory

programmable

write-back/write-through,

caching-

inhibited/caching-allowed,

and

memory

coherency

enforced/memory

coherency not enforced on a page or block basis

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Separate IBATs and DBATs (eight each) also defined as SPRs

PC7447 Datasheet(PDF) 7 Page - ATMEL Corporation

PC7447 Datasheet(HTML) 7 Page - ATMEL Corporation

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