PC7447 datasheet(8/66 Pages) ATMEL

8 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

–

Separate instruction and data translation lookaside buffers (TLBs)

Both

TLBs

are

128-entry,

two-way

set-associative,

and

use

LRU

replacement algorithm

TLBs are hardware- or software-reloadable (that is, on a TLB miss a page

table search is performed in hardware or by system software)

•

Efficient data flow

–

Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows

up to 256 bits

–

The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the

VRs

–

L2 cache is fully pipelined to provide 256 bits per processor clock cycle to

the L1 cache

–

As many as eight outstanding, out-of-order, cache misses are allowed

between the L1 data cache and L2/L3 bus

–

As many as 16 out-of-order transactions can be present on the MPX bus

–

Store merging for multiple store misses to the same line. Only coherency

action taken (address-only) for store misses merged to all 32 bytes of a

cache block (no data tenure needed)

–

Three-entry finished store queue and five-entry completed store queue

between the LSU and the L1 data cache

–

Separate additional queues for efficient buffering of outbound data (such as

castouts and write-through stores) from the L1 data cache and L2 cache

•

Multiprocessing support features include the following:

–

Hardware-enforced, MESI cache coherency protocols for data cache

–

Load/store with reservation instruction pair for atomic memory references,

semaphores, and other multiprocessor operations

•

Power and thermal management

–

1.6V processor core

–

The following three power-saving modes are available to the system:

Nap—Instruction fetching is halted. Only those clocks for the time base,

decrementer, and JTAG logic remain running. The part goes into the doze

state to snoop memory operations on the bus and then back to nap using a

QREQ/QACK processor-system handshake protocol

Sleep—Power consumption is further reduced by disabling bus snooping,

leaving only the PLL in a locked and running state. All internal functional

units are disabled

Deep sleep— When the part is in the sleep state, the system can disable the

PLL. The system can then disable the SYSCLK source for greater system

power savings. Power-on reset procedures for restarting and relocking the

PLL must be followed on exiting the deep sleep state

PC7447 Datasheet(PDF) 8 Page - ATMEL Corporation

PC7447 Datasheet(HTML) 8 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL