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PC7447 Datasheet(PDF) 30 Page - ATMEL Corporation |
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PC7447 Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 66 page ![]() 30 PC7457/47 [Preliminary] 5345B–HIREL–02/04 Figure 13 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs. Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking. {L3DATA[0:15], L3DP[0:1]} {L3DATA[16:31], L3DP[2:3]} {L3DATA[32:47], L3DP[4:5]} L3ADDR[18:0] L3_CNTL[0] L3_CLK[0] L3_CLK[1] L3_ECHO_CLK[0] L3_ECHO_CLK[1] L3ECHO_CLK[2] L3_ECHO_CLK[3] {L3DATA[48:63], L3DP[6:7]} CQ SA[18:0] CK B1 B2 SRAM 0 SRAM 1 CQ D[0:17] D[18:35] CQ SA[18:0] CK B1 B2 CQ D[0:17] D[18:35] L3_CNTL[1] NC NC GND GND GND NC NC GND GND GND PC7457 Denotes Receive (SRAM to PC7457) Aligned Signals Denotes Transmit (PC7457 to SRAM) Aligned Signals (1) CQ CK B3 G CQ LBO CQ CK B3 G CQ LBO GVDD/2 (1) GVDD/2 |
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