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PC7447 Datasheet(PDF) 51 Page - ATMEL Corporation |
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PC7447 Datasheet(HTML) 51 Page - ATMEL Corporation |
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51 / 66 page ![]() 51 PC7457/47 [Preliminary] 5345B–HIREL–02/04 System Design Information This section provides system and thermal design recommendations for successful appli- cation of the PC7457. PLL Configuration The PC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PC7457 is shown in Table 18 for a set of exam- ple frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that don’t comply with the 1 GHz column in Table 8 on page 20. Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts PLL_CFG[0:4] Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) Bus-to-Core Multiplier Core-to-VCO Multiplier Bus (SYSCLK) Frequency 33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz 01000 2x 2x 10000 3x 2x 10100 4x 2x 667 (1333) 10110 5x 2x 667 (1333) 835 (1670) 10010 5.5x 2x 733 (1466) 919 (1837) 11010 6x 2x 600 (1200) 800 (1600) 1002 (2004) 01010 6.5x 2x 650 (1300) 866 (1730) 1086 (2171) 00100 7x 2x 700 (1400) 931 (1862) 1169 (2338) 00010 7.5x 2x 623 (1245) 750 (1500) 1000 (2000) 1253 (2505) 11000 8x 2x 600 (1200) 664 (1328) 800 (1600) 1064 (2128) 01100 8.5x 2x 638 (1276) 706 (1412) 850 (1700) 1131 (2261) 01111 9x 2x 600 (1200) 675 (1350) 747 (1494) 900 (1800) 1197 (2394) 01110 9.5x 2x 633 (1266) 712 (1524) 789 (1578) 950 (1900) 1264 (2528) 10101 10x 2x 667 (1333) 750 (1500) 830 (1660) 1000 (2000) 10001 10.5x 2x 700 (1400) 938 (1876) 872 (1744) 1050 (2100) |
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