MMPF0100Z datasheet(102/128 Pages) NXP

102 / 128 page

102

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.5.6

The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can

be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,

the functional registers are the same, but the extended registers are different. To access registers in Table 136. Extended page 1, page

106, one must first write 0x01 to the page register at address 0x7F, and to access registers Table 137. Extended page 2, page 110, one

must first write 0x02 to the page register at address 0x7F. To access the Table 135. Functional page, page 103 from one of the extended

pages, no write to the page register is necessary.

Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The contents

of all registers are given in the tables defined in this chapter; each table is structure as follows:

Name: Name of the bit.

Bit #: The bit location in the register (7-0)

R/W: Read / Write access and control

• R is read-only access

• R/W is read and write access

• RW1C is read and write access with write 1 to clear

Reset: Reset signals are color coded based on the following legend.

Default: The value after reset, as noted in the default column of the memory map.

• Fixed defaults are explicitly declared as 0 or 1.

• “X” corresponds to Read / Write bits initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are

subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies.

For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the

interrupts.

Table 133. Register MEMC ADDR 0x1E

Name

Bit #

R/W

Default

Description

MEMC

7:0

R/W

Memory bank C

Table 134. Register MEMD ADDR 0x1F

Name

Bit #

R/W

Default

Description

MEMD

7:0

R/W

Memory bank D

Bits reset by SC and VCOREDIG_PORB

Bits reset by PWRON or loaded default or OTP configuration

Bits reset by DIGRESETB

Bits reset by PORB or RESETBMCU

Bits reset by VCOREDIG_PORB

Bits reset by POR or OFFB

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