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AXP288D Datasheet(PDF) 74 Page - Shenzhen X-Powers Technology Co ., Ltd |
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AXP288D Datasheet(HTML) 74 Page - Shenzhen X-Powers Technology Co ., Ltd |
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74 / 110 page  AXP288 PMIC Optimized For Multi-Core High-Performance System AXP288 Datasheet V1.06 Copyright © 2014 X-Powers Limited. All Rights Reserved. 74 REG 2CH: BC Module Global Register Default：00H Reset: bit7 is system reset, bit[6:0] Power On reset Table 10-30 Bit Description R/W Default 7 DCD_SEL DCD Detect Select Software writes 1 to this bit to select DCD Detection during BC Detect. RW 0 6-5 DCD_TIMEOUT_CTL DCD Timeout Control Software writes these fields to configure the DCD timeout value. When the DCD_SEL is set, the BC Module read the MultValIdBc if pin contact has been detected or the time defined on these fields has been expired . When the DCD_SEL is not set, he BC Module read the MultValIdBc if the time defined on these fields has been expired . 00: 300ms 01: 100ms 10: 500ms 11: 900ms RW 0 4 Vlgc_Com_Sel Vlgc Compare Select Software writes 1 to this bit to choose the Vlgc compare during Primary Detect when the ID pin is float. When this bit is set, the BC Module is optionally allowed to compare D- with Vlgc beside the Vdp_src comparing. The BC Module determine that it is attached to a DCP or CDP if D- is greater than Vdat_ref, but less than Vlgc. Otherwise, the BC Module determine that it is attached to a SDP, which may actually be a SDP, or a PS2 port, or a proprietary charge. RW 0 3 DBP_Timeout_CTL DBP Hardware Timeout Control If this bit is set, the BC Module would clear the DB_Perform bit on the BC_USB_Sta_R register after Tsvld_con_wkb when the DB_Perform bit is set. Note: Tsvld_con_wkb = 45min RW 0 2 BC_status BC Detection status Detection finish or not 1:Detecting,when starting BC Detect, set this bit 0:Detect finish RW 0 1 Reserved RW 0 0 RS RW 0 |
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