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AXP288D Datasheet(PDF) 29 Page - Shenzhen X-Powers Technology Co ., Ltd

Part # AXP288D
Description  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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Manufacturer  XPOWER [Shenzhen X-Powers Technology Co ., Ltd]
Direct Link  http://www.x-powers.com/en.php/Index/index
Logo XPOWER - Shenzhen X-Powers Technology Co ., Ltd

AXP288D Datasheet(HTML) 29 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
29
LDO 6 - eMMC
Buck2- VNN
Buck3 -V1P05A/
V1P15
Buck4 -VDDQ
Buck6 -V1P8A
LD03 -V3P3A
RSMRST_B
DRAMPWROK
Buck5 - VGG
Buck1 - VCC
CHT Cold Boot Sequence
VCCAPWROK
COREPWROK
LDO1 -V1P2A
VBAT
VRTC
SUSPWRDNACK
PLTRST_B
SLP_S0IX_B
Signals from SoC
T0
T1
T2
T3
T4
T5
T7
T6
T8
LDO5 - VREFDQ
Figure 9-7
Note:
•
Buck6 and LDO1 power up at the same time
•
LDO6 and LDO3 can power up at the same time
•
PMIC Power up sequence has no dependency on SUSPWRDNAK signal
•
SLP_S0IX_B signal gates pmic performing the remainder power up sequence
Table 9-4
Parameter
Description
Min
Typical
Max
Units
T0
BUCK2 to BUCK3 turn on delay
Buck2 to Buck3 turn on delay should
follow the standard delay (T1), but have an
option to support no delay (to be
compliant with CHV A0)
μs
T1
Rail to Subsequent Rail Turn-On
Delay for all rails unless specified
otherwise
0.01
1
2.0
ms



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