HY27SF161G2M-VIP datasheet(8/48 Pages) HYNIX

8 / 48 page

Rev 0.7 / Apr. 2005

Preliminary

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name

Description

IO0-IO7

IO8-IO15(1)

DATA INPUTS/OUTPUTS

The IO pins allow to input command, address and data and to output data during read / program

operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to

High-Z when the device is deselected or the outputs are disabled.

CLE

COMMAND LATCH ENABLE

This input activates the latching of the IO inputs inside the Command Register on the Rising edge of

Write Enable (WE#).

ALE

ADDRESS LATCH ENABLE

This input activates the latching of the IO inputs inside the Address Register on the Rising edge of

Write Enable (WE#).

CE#

CHIP ENABLE

This input controls the selection of the device. When the device is busy CE# low does not deselect

the memory.

WE#

WRITE ENABLE

This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise

edge of WE#.

RE#

READ ENABLE

The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data

is valid tREA after the falling edge of RE# which also increments the internal column address counter

by one.

WP#

WRITE PROTECT

The WP# pin, when Low, provides an Hardware protection against undesired modify (program /

erase) operations.

RB#

READY BUSY

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

VCC

SUPPLY VOLTAGE

The VCC supplies the power for all the operations (Read, Write, Erase).

VSS

GROUND

NOT CONNECTED

PRE

To Enable Power On Auto Read. When PRE is a logic high, Power on Auto Read mode is enabled, and

when PRE is a logic low, Power Auto Read mode is disabled. Power On Auto Read mode is available

only on 3.3V device.

Not using POWER-ON AUTO-READ, connect it Vss or leave it N.C.

Table 2: Pin Description

NOTE:

1. For x16 version only

2. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required

during program and erase operations.

HY27SF161G2M-VIP Datasheet(PDF) 8 Page - Hynix Semiconductor

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