LS1020A datasheet(28/71 Pages) FREESCALE

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Architecture

TWR-LS1021A Reference Manual, Rev. 0

Freescale Semiconductor

2-13

2.9

Ethernet controllers

The TWR-LS1021A supports three Ethernet Controllers (EC) which can connect to Ethernet PHYs using

MII or RGMII protocols. The EC3 port can operate in RGMII mode and is always on, while the EC2 and

EC3 ports only operates in SGMII mode. All three ports connects to Atheros AR8033 PHYs

Connections and routing for the TSEC are summarized in Table 2-9.

The drives the and associated PHY devices with a 125.00 MHz clock, from one of various sources. See

Section 2.6 for details on Ethernet clocking.

2.10

Ethernet management interface

The EMI routing architecture is shown in Figure 2-8.

Table 2-9. Ethernet port locations

EC #

Mode

Interface

voltage

PHY

address

Connector location

Status indicator

SGMII

S1VDD/X1VDD

(1.0V/1.35V)

P1 Bottom

R: Transmit or Receive activity

L: Link (1000M)

SGMII

S1VDD/X1VDD

(1.0V/1.35V)

P1 Top

R: Transmit or Receive activity

L: Link (1000M)

RGMII

LVDD

(2.5V)

U20

L: Transmit or Receive activity

R: Link (Any speed)

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