LS1020A datasheet(62/71 Pages) FREESCALE

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CPLD System Controller Architecture

TWR-LS1021A Reference Manual, Rev. 0

Freescale Semiconductor

4-5

0x04

R/W

CPLD override physical switches Enable

Bit [0]: RCW Source Location control

(Register 0x05 and 0x06 cfg_rcw_src)

output enable

0 Disable (Default)

1 Enable

Bit [1]: I2C3/IFC_CS2/CS3_B (Register

0x09 bit[0]) output enable

0 Disable (Default)

1 Enable

Bit [2]: SPI2/LPUART and LCD (Register

0x0A bit[0]) output enable

0 Disable (Default)

1 Enable

Bit [3]: CAN3/USB2 Interface Selection

(Register 0x0B bit[0]) output enable

0 Disable (Default)

1 Enable

Bit [4]: LCD/QE Selection (Register 0x0C

bit[0]) output enable

0 Disable (Default)

1 Enable

Bit [5]: SerDes Lane mux Selection (Register

0x0d bit[0:3]) output enable

0 Disable (Default)

1 Enable

Bit [6]: Flash bank selection (Register 0x07

vbank) output enable

0 Disable (Default)

1 Enable

Bit[7]: ELEV connector EBI_CS0 selection

(Register 0x0F bit[0:2]) output enable

0 Disable (Default)

1 Enable

soft_mux_on1

0x00

0x05

R/W

POR RCW source location Control/Status

Bit [0:7]: cfg_rcw_src[0:7]

cfg_rcw_src1

Actual pins

status of

cfg_rcw_src[0:7]

on POR

0x06

R/W

POR RCW source location Control/Status

Bit [0]: cfg_rcw_src[8]

cfg_rcw_src2

Actual pin status

cfg_rcw_src[8]

on POR

0x07

R/W

Flash bank selection Control Register

Bit [0]: 0 upper bank (bank0) for booting

1 lower bank (bank1) for booting

Bit [7:1]: Reserved

vbank

SW3[5]-BANK_

SEL

Table 4-3. CPLD BCSR register detail map

Base Address

Offset

Access

Type

Description

Default Value

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