AX58100 datasheet(10/71 Pages) ASIX

10 / 71 page

AX58100

EtherCAT Slave Controller

Signal Description

Following abbreviations are used in “Type” column of below pin description tables. Note that some I/O pins with

multiple signal definitions on the same pin may have different attributes in “Type” column for different signal

definition.

Analog Bi-directional I/O

Internal Pull-Up (75K)

Analog Input

Internal Pull-Down (75K)

Analog Output

Power/Ground pin

Bi-directional I/O, 3.3V with 5V tolerant

Schmitt Trigger

Input, 3.3V with 5V tolerant

Tri-state

Output, 3.3V with 5V tolerant

4mA driving strength

Input, 3.3V

8mA driving strength

Output, 3.3V

For example, pin 6 in AX58100 package can be LAT_IN, MISO or LRDY. If LAT_IN is selected, its Type is I5; if

MISO or LRDY is selected, its Type is O5 or O5/T. In other words, the T (tri-state) only takes effect in

LRDYsignal mode while LT_IN and MISO signal mode doesn’t. Users should refer to the table specific to the

desired function for exact pin type definition.

The multi-function pin settings are configured by the I2C Hardware Configuration EEPROM (HWCFGEE). Please

refer to Section 3.2 in detailed.

1.4.1

General

Pin Name

Type

Pin No

Pin Description

TEST

I5/PD/S

Test mode enable

For normal operation, please always tie to logic low or NC.

RSTn

I5/PU/S

Reset Input, active low

RST_N is the hardware reset input used to reset this chip. This input is AND

with internal Power-On-Reset (POR) circuit, which generates the main

system reset for this chip

RSTO

O5/8m

Reset Output

XSCI

Crystal 25MHz Input

XSCO

Crystal 25MHz Output

SCL

O5/T/4m/

I2C Serial Clock line for I2C master controller.

SCL is a tri-stateable output, which requires an external pull-up resistor.

SDA

B5/T/4m/

I2C Serial Data line for I2C master controller.

SDA is a tri-stateable output, which requires an external pull-up resistor.

PDI_EMU

PDI Emulation enable

EEP_DONE

O5/8m

EEPROM is loaded, PDI is active

LED_RUN\

EEP_SIZE

B5/4m

RUN LED

This pin is input direction during chip reset stage used to bootstrap the mode

setting to decide the EEPROM size configuration, please refer to Section 3.1

LED_ERR\

3PORT_MODE

B5/4m

Error LED

This pin is input direction during chip reset stage used to bootstrap the mode

setting to decide the Port 2 MII enable configuration, please refer to Section

3.1

SYNC_LATCH[0] B5/8m

Distributed Clocks SyncSignal output or LatchSignal input 0

SYNC_LATCH[1] B5/8m

Distributed Clocks SyncSignal output or LatchSignal input 1

Reserved. Please connect to GND.

Table 1-1: Common Pin Description

AX58100 Datasheet(PDF) 10 Page - ASIX Electronics Corporation

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