AX58100 datasheet(68/71 Pages) ASIX

68 / 71 page

AX58100

EtherCAT Slave Controller

Symbol

Description

Min

Typ

Max Units

Clock

TSCLK

MSCLK Period

TSCLKH +

TSCLKL

TSCLKH

MSCLK high

5 * Divide

TSCLKL

MSCLK low

5 * Divide

Bus Timing

TDBS1

MSS[x] to MSCLK (Mode0/1 without DBS1K)

(DBS + 1) * Tsclk

MSS[x] to MSCLK (Mode2/3 without DBS1K)

(DBS + 0.5) * Tsclk

MSS[x] to MSCLK (Mode0/1 with DBS1K)

((1024 * (DBS + 1)) + 1) *

Tsclk

MSS[x] to MSCLK (Mode2/3 with DBS1K)

((1024 * (DBS + 1)) + 0.5) *

Tsclk

TDBS2

Byte to byte (Mode0/1 without DBS1K)

(DBS + 0.5) * Tsclk

Byte to byte (Mode2/3 without DBS1K)

(DBS + 0.5) * Tsclk

Byte to byte (Mode0/1 with DBS1K)

((1024 * (DBS + 1)) + 0.5) *

Tsclk

Byte to byte (Mode2/3 with DBS1K)

((1024 * (DBS + 1)) + 0.5) *

Tsclk

TDBS3

MSCLK to MSS[x] (Mode0/1 without DBS1K)

(DBS + 0.5) * Tsclk

MSCLK to MSS[x](Mode2/3 without DBS1K)

(DBS + 1.0) * Tsclk

MSCLK to MSS[x](Mode0/1 with DBS1K)

((1024 * (DBS + 1)) + 0.5) *

Tsclk

MSCLK to MSS[x](Mode2/3 with DBS1K)

((1024 * (DBS + 1)) + 1.0) *

Tsclk

TDT1

MSS[x] gap (without DT1K)

(DT + 2) * Tsclk

MSS[x] gap (with DT1K)

(1024 * (DT + 1) + 2) * Tsclk

TMISET

MMISO setup time

10.5

TMIHD

MMISO hold time

TMODLY

MMOSI output delay

0.5

TRT

MDRLD ready timeout (RDY mode)

(1 + SPIRPT) * 1024 * Tsclk

TPT

MTRG timeout

(1 + SPIRPT) * 1024 * Tsclk

TLDACG

MDRLD Gap (LDAC mode)

((LDACG1K * 1023) + 1) *

(LDGAP + 1) * Tsclk

TLDACW

MDRLD Width (LDAC mode)

(LDACG1K * 1023 + 1) *

(LDWID + 1) * Tsclk

Table 4-21: SPI Master Timing Table

AX58100 Datasheet(PDF) 68 Page - ASIX Electronics Corporation

AX58100 Datasheet(HTML) 68 Page - ASIX Electronics Corporation

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