AX58200BT datasheet(86/180 Pages) ASIX

86 / 180 page

AX58200

EtherCAT Slave Controller SoC

Controller Area Network (CAN)

2.28.1 Overview

The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module

Interface. The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The

bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer, additional

transceiver hardware is required.

For communication on a CAN network, individual Message Objects are configured. The Message Objects and

Identifier Masks for acceptance filtering of received messages are stored in the Message RAM. All functions

concerning the handling of messages are implemented in the Message Handler. These functions include

acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of

transmission requests as well as the generation of the module interrupt.

The register set of the C_CAN can be accessed directly by the software through the module interface. These

registers are used to control/configure the CAN Core and the Message Handler and to access the Message RAM.

2.28.2 Features

⚫

Supports CAN protocol version 2.0 part A and B

⚫

Bit rates up to 1 MBit/s

⚫

32 Message Objects

⚫

Each Message Object has its own identifier mask

⚫

Programmable FIFO mode (concatenation of Message Objects)

⚫

Maskable interrupt

⚫

Disabled Automatic Re-transmission mode for Time Triggered CAN applications

⚫

Programmable loop-back mode for self-test operation

⚫

16-bit module interfaces to the AMBA APB bus

⚫

Supports wake-up function

Secure Digital Host Controller (SDH)

2.29.1 Overview

The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a DMA

(Direct Memory Access) function for SD to exchange data between system memory and shared buffer (128

bytes), and the SD unit controls the interface of SD/SDHC. The SDHOST controller can support SD/SDHC and

cooperated with DMAC to provide a fast data transfer between system memory and cards.

2.29.2 Features

⚫

AMBA AHB master/slave interface compatible, for data transfer and register read/write.

⚫

Supports single DMA channel.

⚫

Supports hardware Scatter-Gather function.

⚫

Using single 128 Bytes shared buffer for data exchange between system memory and cards.

⚫

Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).

⚫

Interface with DMAC for register read/write and data transfer.

⚫

Supports SD/SDHC card.

⚫

Completely asynchronous design for Secure Digital with two clock domains, HCLK and Engine

clock, note that frequency of HCLK should be higher than the frequency of peripheral clock.

AX58200BT Datasheet(PDF) 86 Page - ASIX Electronics Corporation

AX58200BT Datasheet(HTML) 86 Page - ASIX Electronics Corporation

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