AX58200BT datasheet(81/180 Pages) ASIX

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AX58200

EtherCAT Slave Controller SoC

SPI Synchronous Serial Interface Controller (SPI Master mode)

2.22.1 Overview

The SPI Synchronous serial Interface Controller for SPI master mode performs a serial-to-parallel conversion on

data received from the peripheral, and a parallel-to-serial conversion on data received from MCU. This SPI

controller can drive one external peripheral (External SPI Flash) and it is seen as the SPI master mode. It can

generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag.

The active level of device/slave select signal can be chosen to low active or high active, which depends on the

peripheral. Writing a divisor into the SPIM_CTL1 register can program the frequency of serial clock output to

the peripheral.

In SPI Flash controller, normal I/O mode contains four 32-bit transmit/receive buffers, and can provide 1 to 4

burst mode operation. The number of bits in each transaction can be 8, 16, 24, or 32; data can be

transmitted/received up to four successive transactions in one transfer.

By DMA write mode, user can move data from SRAM to external SPI Flash component. In DMA read mode,

user can move data from external SPI Flash component to SRAM. In direct memory mapping mode (DMM

mode), this SPI Flash controller will translate the AHB bus commands into SPI Flash operations without MCU

setting related SPI Flash command. Therefore, users can access external SPI Flash as a ROM module.

In direct memory mapping mode with cache off mode, it will pre-fetch 4-word Flash data after a direct memory

mapping access. When using direct memory mapping mode with cache on mode, it will use 32 Kbytes cache

memory to reduce the number of accessing external SPI Flash component and the performance of SPI Flash

access can be improved. To improve the read operation of SPI Flash without increasing the serial clock

frequency, this SPI Flash controller supports DTR/DDR (Double Transfer Rate/Double Data Rate) read

command codes that support Standard/Dual/Quad SPI modes. The one byte command code is still latched into

the device on the rising edge of the serial clock similar to all other SPI commands. Once a DTR/DDR instruction

code is accepted by the device, the address input and data output will be latched on both rising and falling edges

of the serial clock.

In core coupled memory mode (CCM mode), the cache function is disabled by hardware automatically, and

MCU can access this 32 Kbytes cache memory as general SRAM. For data protection, this SPI Flash controller

supports cipher encryption and decryption circuits to protect data which user places into external SPI Flash when

DMA read/write mode and direct memory mapping mode are used.

2.22.2 Features

⚫

Supports maximum 32M bytes SPI Flash size

⚫

Supports SPI master mode

⚫

Supports Direct Memory Mapping Mode and Normal I/O Mode

⚫

Supports 8/16/24/32 bits transaction for Normal I/O mode

⚫

Provides burst mode operation in Normal I/O mode, which can transmit/receive data up to four

successive transactions in one transfer

⚫

Supports DMA mode read/write

⚫

Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode

⚫

Supports Double Transfer Rate (DTR) / Double Data Rate (DDR) transfer mode

⚫

Supports 32 Kbytes cache memory

⚫

Supports 32 Kbytes Core Coupled Memory (CCM) when cache function disable

⚫

Supports Cipher encryption/decryption

⚫

One slave/device select line for external SPI Flash component

AX58200BT Datasheet(PDF) 81 Page - ASIX Electronics Corporation

AX58200BT Datasheet(HTML) 81 Page - ASIX Electronics Corporation

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