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AX58200BT Datasheet(PDF) 56 Page - ASIX Electronics Corporation |
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AX58200BT Datasheet(HTML) 56 Page - ASIX Electronics Corporation |
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56 / 180 page  56 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC 1 0 CLK_PLLCTL[19] HIRC 12MHz HXT 4~24MHz PLL FOUT 111 011 010 001 HXT LXT HXT HCLK HIRC 000 1/2 1/2 1/2 CLK_CLKSEL0[5:3] 1 0 SysTick RTC WDT CPU LXT 32.768 kHz LIRC 10 kHz 011 010 001 PLLFOUT LXT HXT LIRC 000 CLK_CLKSEL0[2:0] SYST_CTRL[2] CPUCLK 1/(HCLKDIV+1) LIRC LIRC 11 10 CLK_CLKSEL1[1:0] HCLK 1/2048 HIRC HXT 01 LXT 111 HIRC 1 0 LXT CLK_CLKSEL3[8] EADC 1/(EADCDIV+1) PCLK1 WWDT 11 10 CLK_CLKSEL1[31:30] HCLK 1/2048 /1,/2,/4,/8,/16 USBH HSUSBH HSUSBD SPIM CRYP SD1 SD0 PDMA FMC EBI CRC PCLK0 EPWM0 OPA I2S I2C2 I2C0 ECAP0 CAN0 BPWM0 UR0 TMR1 TMR0 QSPI0 SC2 SC0 QEI0 USCI0 USBD UR4 UR2 WDG SPI1 SPI3 EMC Ethernet 1/(EMACDIV+1) REFCLK MDCCLK 1/2 1/20 EMC RX_CLK TX_CLK HCLK PLLFOUT LIRC HCLK HXT HIRC PLLFOUT CLK_CLKSEL0[21:20] 11 10 01 00 1/(SDH0DIV+1) 1/(SDH1DIV+1) SD0 SD1 CLK_CLKSEL0[23:22] CLK_CLKSEL1[29:28] HCLK HXT HIRC LXT 11 10 01 00 /2 (CLK_CLKOCTL[3:0]+1) CLKO 0 1 DIV1EN (CLK_CLKOCTL[5]) 0 1 CLK1HZEN (CLK_CLKOCTL[6]) 1 Hz clock from RTC 0 1 LXT LIRC RTCSEL(CLK_CLKSEL3[8]) /32768 CLK_CLKSEL2[3:2] CLK_CLKSEL2[7:6] CLK_CLKSEL2[13:12] PCLK0 HXT HIRC PLLFOUT 11 10 01 00 1/(QSPI0_CLKDIV[8:0]+1) 1/(SPI1_CLKDIV[8:0]+1) 1/(SPI3_CLKDIV[8:0]+1) QSPI0 SPI1 SPI3 CLK_CLKSEL2[5:4] CLK_CLKSEL2[11:10] PCLK1 HXT HIRC PLLFOUT 11 10 01 00 1/(SPI0_CLKDIV[8:0]+1) 1/(SPI2_CLKDIV[8:0]+1) SPI0 SPI2 EPWM 0 1 0 PLLFOUT PCLK0 CLK_CLKSEL2[0] CLK_CLKSEL2[8] BPWM 0 EPWM 1 1 0 PLLFOUT PCLK1 CLK_CLKSEL2[1] CLK_CLKSEL2[9] BPWM 1 SC0 PCLK0 HXT HIRC PLLFOUT CLK_CLKSEL3[1:0] CLK_CLKSEL3[5:4] 11 10 01 00 1/(SC0DIV+1) 1/(SC2DIV+1) SC2 SC1 PCLK0 HXT HIRC PLLFOUT CLK_CLKSEL3[3:2] 11 10 01 00 1/(SC1DIV+1) I2S PCLK0 HXT HIRC PLLFOUT CLK_CLKSEL3[17:16] 11 10 01 00 111 010 001 000 PCLK0 LXT HXT HIRC CLK_CLKSEL1 [10:8] CLK_CLKSEL1[14:12] 101 LIRC 011 TM0/TM1 TMR0 TMR1 111 010 001 000 PCLK1 LXT HXT HIRC 101 LIRC 011 TM2/TM3 TMR2 TMR3 CLK_CLKSEL1 [18:16] CLK_CLKSEL1[22:20] HCLK SRAM PCLK1 OTG I2C1 ECAP1 DAC CAN1 BPWM1 EADC ACMP UR3 UR1 TMR3 RTC QEI1 EPWM1 HSOTG SPI0 USCI1 UR5 SC1 TMR2 SPI2 /1,/2,/4,/8,/16 UART0 LXT HXT HIRC PLLFOUT CLK_CLKSEL1[25:24] CLK_CLKSEL1[27:26] CLK_CLKSEL3[25:24] CLK_CLKSEL3[27:26] CLK_CLKSEL3[29:28] CLK_CLKSEL3[31:30] 11 10 01 00 1/(UART0DIV+1) 1/(UART1DIV+1) 1/(UART2DIV+1) 1/(UART3DIV+1) 1/(UART4DIV+1) 1/(UART5DIV+1) UART1 UART2 UART3 UART4 UART5 USB1.1 Host Controller USB2.0 OTG Controller USB2.0 Device Controller USB1.1 Device Controller USB2.0 OTG PHY PLLFOUT USB1.1 OTG Controller USB2.0 Host Controller 30MHz USB1.1 OTG PHY 48MHz /(USBDIV + 1) HXT Note: For USB High-speed application, HXT should be 12 MHz. Figure 2.3-1: Clock Generator Global View Diagram |
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