AX58200BT datasheet(91/180 Pages) ASIX

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AX58200

EtherCAT Slave Controller SoC

High Speed USB On-The-Go (HSOTG)

2.35.1 Overview

The HSOTG controller interfaces to USB PHY and USB controllers which consist of a USB 2.0 host controller

and a USB 2.0 HS device controller. The OTG controller supports HNP and SRP protocols defined in the “On-

The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3 Specification”.

USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only, Device-only,

ID-dependent or OTG Device mode defined in HSUSBROLE (SYS_USBPHY[17:16]). In Host-only mode,

USB frame acts as USB host. USB frame can support high-speed, full-speed and low- speed transfer. In Device-

only mode, USB frame acts as USB device. USB frame supports high-speed and full-speed transfer. In ID-

dependent mode, USB frame can be USB Host or USB device depends on USB_ID pin state. In OTG device

mode, the role of USB frame depends on the definition of OTG specification. USB frame supports high-speed

and full-speed transfer when OTG device acts as a peripheral.

2.35.2 Features

⚫

Built in USB PHY

⚫

Configurable to operate as:

–

Host-only

–

Device-only

–

ID-dependent: The role of USB frame is only dependent on USB_ID pin value--as USB Host

(USB_ID pin is low) or USB Device (USB_ID pin is high). Not support HNP or SRP protocol.

–

OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is low) or B-

device (USB_ID pin is high). Support HNP and SRP protocols.

CRC Controller (CRC)

2.36.1 Overview

The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common polynomials

CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.

2.36.2 Features

⚫

Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32

–

CRC-CCITT: X16 + X12 + X5 + 1

–

CRC-8: X8 + X2 + X + 1

–

CRC-16: X16 + X15 + X2 + 1

–

CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

⚫

Programmable seed value

⚫

Supports programmable order reverse setting for input data and CRC checksum

⚫

Supports programmable 1’s complement setting for input data and CRC checksum

⚫

Supports 8/16/32-bit of data width

–

8-bit write mode: 1-AHB clock cycle operation

–

16-bit write mode: 2-AHB clock cycle operation

–

32-bit write mode: 4-AHB clock cycle operation

⚫

Supports using PDMA to write data to perform CRC operation

AX58200BT Datasheet(PDF) 91 Page - ASIX Electronics Corporation

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