CS98200 datasheet(29/60 Pages) CIRRUS

29 / 60 page

DS581PP2

CS98200

Next Generation DVD Processor

5. FUNCTIONAL DESCRIPTION

5.1

RISC Processor

The CS98200 includes two powerful, third-gen-

eration proprietary 32-bit RISC processors,

RISC0 and RISC1, with optimizing C compiler

support and source level debugger. The RISC

processors fully support many Real Time Oper-

ation Systems (RTOS). The DVD application

user interface resides on RISC1 and is customer

programmable. The real time control of low lev-

el DVD functions is performed by RISC0. RISC1

gains access to system resources controlled by

RISC0 via calls through an Applications Pro-

gramming Interface, See the

CS98200 Software

API. All RISC0 firmware, API and sample appli-

cation code are supplied with the CS98200.

The RISC processors also have a MAC engine,

which performs multiply/accumulate in 2 cy-

cles in a pipelined fashion with C support, effec-

tively achieving single cycle throughout. The

RISC0 processor coordinates on-chip multi-

threaded tasks, as well as system activities such

as remote control and front panel control. The

DVD application end-user interface resides on

RISC1, and any modifications to that interface

occur through the CS98200 API.

5.2

DSP Processor

The CS98200 contains a proprietary digital sig-

nal processor (DSP), which is optimized for au-

dio applications. The DSP performs 32-bit

simple integer operations, and has a 24-bit fixed

point logic unit, with a 54-bit accumulator. The

multiply-accumulator has single-cycle through-

put, with two cycle latency. The DSP is opti-

mized

for

bit

packing

and

unpacking

operations. The interface to main memory is de-

signed for handling flexible block sizes and skip

counts.

5.3

Memory Control

The DRAM Interface performs the SDRAM con-

trol and arbitration functions for all the other

modules in the CS98200. The DRAM interface

services and arbitrates a number of clients and

stores their code and/or data within the local

memory. This arbitration and scheduling guar-

antees the allocation of sufficient bandwidth to

the various clients. The DRAM Interface sup-

ports up to 32 Mbytes. For a typical DVD player

application, CS98200 requires 8 Mbytes memo-

ry space.

Sharing the same interface, CS98200 also sup-

ports FLASH ROM, OTP, or mask ROM inter-

face. Code is stored in ROM. After the system is

booted, the code is shadowed inside SDRAM

for execution. The FLASH ROM interface is pro-

vided so that the code can be upgraded in the

field once the communications channel is estab-

lished. Utility software will be provided to de-

bug and upgrade code for the system

manufacturer.

5.4

Dataflow Control (DMA)

The DMA controller moves data between the

external memory and internal memory. The ex-

ternal memory address can be specified using a

address registers. Separate start/end address

registers are used for DMA read and write oper-

ations. The DMA interface also has a block

transfer function, which allows for the transfer

of one block of data from one external memory

location to another external memory location. In

effect, this feature combines a DMA read and

write into one operation. In addition, the DMA

write operation allows for byte, short, word,

and other types of masking.

5.5

System Control Functions

The system control functions are used to coordi-

nate the activities of the multiple processors,

and to provide the supporting system opera-

tions. Eight 32-bit communication registers are

available for inter-processor communication,

and 32 semaphore registers are used for re-

source locking. Timers are available for general-

purpose functions, as well as more specialized

CS98200 Datasheet(PDF) 29 Page - Cirrus Logic

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