F4481 Datasheet

© 2020 Renesas Electronics Corporation

4

December 15, 2020

Figure 47. K Factor.............................................................................................................................................................................................29

Figure 48. Inter/Intra Channel Isolation at DSA = 0dB........................................................................................................................................29

Figure 49. Supply Current...................................................................................................................................................................................29

Figure 50. Noise Figure at DSA = 0dB ...............................................................................................................................................................29

Figure 51. Noise Figure at DSA = 14dB .............................................................................................................................................................30

Figure 52. Noise Figure at DSA = 28dB .............................................................................................................................................................30

Figure 53. Noise Figure vs Channel (DSA = 0dB)..............................................................................................................................................30

Figure 54. OIP3 at DSA = 0dB...........................................................................................................................................................................30

Figure 55. OIP3 at DSA = 4dB...........................................................................................................................................................................30

Figure 56. OIP3 at DSA = 14dB.........................................................................................................................................................................30

Figure 57. OIP3 at DSA = 28dB.........................................................................................................................................................................31

Figure 58. OIP3 vs Channel (DSA = 0dB).........................................................................................................................................................31

Figure 59. OP1dB at DSA = 0dB.......................................................................................................................................................................31

Figure 60. OP1dB at DSA = 4dB......................................................................................................................................................................31

Figure 61. OP1dB at DSA = 14dB.....................................................................................................................................................................31

Figure 62. OP1dB at DSA = 28dB.....................................................................................................................................................................31

Figure 63. OP1dB vs Channel (DSA = 0dB)......................................................................................................................................................32

Figure 64. Register Bit Map for Each Channel ...................................................................................................................................................33

Figure 65. Serial Mode Default Condition upon Initial Power-Up........................................................................................................................34

Figure 66. Timing Diagram Associated with Programming the Serial Register ..................................................................................................35

Figure 67. Serial Register Timing Diagram.........................................................................................................................................................35

Figure 68. Control Pin Interface for Signal Integrity............................................................................................................................................37

Figure 69. Evaluation Kit Top View.....................................................................................................................................................................38

Figure 70. Evaluation Kit Bottom View ...............................................................................................................................................................38

Figure 71. Applications Circuit............................................................................................................................................................................39

List of Tables

Table 1. Pin Descriptions...................................................................................................................................................................................6

Table 2. Absolute Maximum Ratings.................................................................................................................................................................8

Table 3. Recommended Operating Conditions .................................................................................................................................................9

Table 4. Electrical Characteristics – General..................................................................................................................................................10

Table 5. Electrical Characteristics – Band 1 (400MHz to 500MHz)................................................................................................................13

Table 6. Electrical Characteristics – Band 2 (570MHz to 1100MHz)..............................................................................................................17

Table 7. Package Thermal Characteristics......................................................................................................................................................21

Table 8. Channel Select Truth Table...............................................................................................................................................................33

Table 9. DVGA Attenuation Word Truth Table ................................................................................................................................................34

Table 10. SPI Timing Diagram Values for the Serial Mode...............................................................................................................................36

Table 11. STBY Logic Truth Table ....................................................................................................................................................................36

Table 12. Bill of Material (BOM) ........................................................................................................................................................................40