F4481 datasheet(10/45 Pages) RENESAS

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F4481 Datasheet

December 15, 2020

Electrical Characteristics

See the F4481 Applications Circuit. Unless stated otherwise, specifications apply when operated with VCC = +3.3V, TEP = +25°C, fRF = 900MHz,

STBY_A = STBY_B = STBY_C = STBY_D = HIGH, ZS = 100Ω differential, ZL = 50Ω single-ended, maximum gain setting, and output power =

0dBm/tone. EVKit trace and connector losses are de-embedded.

Table 4.

Electrical Characteristics – General

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Logic Input HIGH

VIH

Supports both 1.8V and 3.3V

logic.

1.07 [a]

Logic Input LOW

VIL

0.63

SPI Logic Current

(CSb, CLK, DATA)

ICTL

3.3V logic.

-5

µA

1.8V logic.

-5

Standby Logic Current

(STBY_A, STBY_B, STBY_C, STBY_D)

IIH, IIL

3.3V logic.

µA

1.8V logic.

Supply Current [b]

ICC_4

4 channels on.

520

630

ICC_3

3 channels on.

400

ICC_2

2 channels on.

270

ICC_1

1 channel on.

150

Standby Current

ICC_STBY

All channels off.

Power ON Switching Time

tON

50% STBY to RF output

settled to within ±0.1dB.

1 [c]

µs

Power OFF Switching Time

tOFF

50% STBY to 35dBc reduction

of output power.

1 [c]

µs

Lineup Out-of-Band Rejection at

Max Gain [c]

fREJECTION

Total gain variation over

fRF = 400MHz to 500MHz.

Referred to fRF = 450MHz.

DSA 0dB attenuation.

dBc

Total gain variation over

fRF = 570MHz to 1100MHz.

Referred to fRF = 900MHz.

DSA 0dB attenuation.

4800MHz < fRF < 7000MHz.

Referred to fRF = 900MHz.

DSA 0dB attenuation.

Gain Settling Time [c]

GST

Any 2dB step in the 0dB to

31.5dB range. 50% of CSb to

1% / 99% RF.

0.4

µs

DSA Adjustment Range

GRANGE

31.5

DSA Step Resolution

GSTEP

LSB

0.5

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