 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VSC8221 Datasheet(PDF) 121 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
VSC8221 Datasheet(HTML) 121 Page - Microsemi Corporation |
|
|
121 / 138 page  VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 121 of 123 123 28.5 REFCLK Timing The following specifications are valid only when the VDD33A is at 3.3 V, ±5%. Figure 27. REFCLK AC Timing Table 57. REFCLK Timing Specifications Symbol Min Typ Max Unit Parameter Description & Conditions TREFCLK25 40 ns Reference clock period, PLLMODE = 0 (25 MHz reference). TREFCLK125 8ns Reference clock period, PLLMODE = 1 (125 MHz reference). FSTABiLiTY 100 ppm Reference clock frequency stability (0 °C to 70 °C). TDUTY 40 50 60 % REFCLK duty cycle in both 25 MHz and 125 MHz modes. JREFCLK25, JREFCLK125 300 ps Total jitter of 25 MHz or 125 MHz reference clock (peak-to-peak). tR/F (REFCLK25) 4ns Reference clock rise time, 25 MHz mode (20% to 80%). tR/F (REFCLK125) 1ns Reference clock rise time, 125 MHz mode (20% to 80%). REFCLK 80% 20% t R, tF T REFCLK T DUTY |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
