SC3200 datasheet(68/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

3.4.6

PCI Bus Interface Signals

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

PCICLK

PCI Clock. PCICLK provides timing for all

transactions on the PCI bus. All other PCI

signals are sampled on the rising edge of

PCICLK, and all timing parameters are

defined with respect to this edge.

---

PCICLK0

PCI Clock Outputs. PCICLK0 and PCICLK1

provide clock drives for the system at 33

MHz. These clocks are asynchronous to PCI

signals. There is low skew between all out-

puts. One of these clock signals should be

connected to the PCICLK input. All PCI clock

users in the system (including PCICLK)

should receive the clock with as low a skew

as possible.

FPCI_MON (Strap)

PCICLK1

LPC_ROM (Strap)

AD[31:24]

See

Table 3-3

on page

38.

See

Table 3-5

on page

54.

I/O

Multiplexed Address and Data. A bus

transaction consists of an address phase in

the cycle in which FRAME# is asserted fol-

lowed by one or more data phases. During

the address phase, AD[31:0] contain a physi-

cal 32-bit address. For I/O, this is a byte

address. For configuration and memory, it is

a DWORD address. During data phases,

AD[7:0] contain the least significant byte

(LSB) and AD[31:24] contain the most signifi-

cant byte (MSB).

D[7:0]

AD[23:0]

A[23:0]

C/BE3#

I/O

Multiplexed Command and Byte Enables.

During the address phase of a transaction

when FRAME# is active, C/BE[3:0]# define

the bus command. During the data phase, C/

BE[3:0]# are used as byte enables. The byte

enables are valid for the entire data phase

and determine which byte lanes carry mean-

ingful data. C/BE0# applies to byte 0 (LSB)

and C/BE3# applies to byte 3 (MSB).

D11

C/BE2#

D10

C/BE1#

A10

C/BE0#

A13

INTA#

AE3

D26

PCI Interrupts. The SC3200 provides inputs

for the optional “level-sensitive” PCI inter-

rupts (also known in industry terms as

PIRQx#). These interrupts can be mapped to

IRQs of the internal 8259A interrupt control-

lers using PCI Interrupt Steering Registers 1

and 2 (F0 Index 5Ch and 5Dh).

Note:

If selected as INTC# or INTD# func-

tion(s) but not used, tie INTC# and

INTD# high.

---

INTB#

AF1

C26

---

INTC#

GPIO19+IOCHRDY

INTD#

B22

AA2

IDE_DATA7

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