10

AT25SF321

DS-25SF321–047F–8/2017

6.3

Dual-I/O Read Array (BBh)

The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially

read a continuous stream of data from the device by simply providing the clock signal once the initial starting address

with two bits of address on each clock and two bits of data on every clock cycle.

perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be clocked

into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location

of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be

clocked into the device.

After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being

output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output

on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same

data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO

and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.

When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of

the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the

array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.

The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M4

≠1,0)

6.3.1

Dual-I/O Read Array (BBh) with Continuous Read Mode

The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read Mode

bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-5. The upper nibble of the (M7-4) controls the

length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The

lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling

edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O

command (after CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This

reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is

asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and

then lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset

command can also be used to reset (M7-0) before issuing normal commands.

(SI)

SCK

(SO)

CS

MSB

MSB

23

1

0

10111011

67

5

410 11

9

812

23

21 22

19 20

Opcode

Address Bits

A23-A16

Address Bits

A15-A8 A7-A0

M7-M0

MSB

27

25 26

24

Byte 1

Byte 2