AT25SF321 datasheet(30/48 Pages) DIALOG

30 / 48 page

AT25SF321

DS-25SF321–047F–8/2017

The complete one byte or two bytes of data must be clocked into the device before the CS pin is deasserted, and the CS

pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,

the state of the Status Register bits will not change, memory protection status will not change, and the WEL bit in the

Status Register will be reset back to the logical “0” state

Table 10-4. Write Status Register Format.

Figure 10-3. Write Status Register

10.3 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in Table 10-1 and Table 10-2 can also be written to as volatile bits. During

power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used

during device operation. This gives more flexibility to change the system configuration and memory protection schemes

quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-

volatile bits.

To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction

must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction

will not set the Write Enable Latch bit. It is only valid for the next following Write Status Registers instruction, to change

the volatile Status Register bit values.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRPO

SEC

BP2

BP1

BP0

WEL

RDY/BSY

SCK

MSB

00000001

410 11

819

17 18

Opcode

DDDD

Status Register In - Byte 1

MSB

21 22

14 15

DDDD

Status Register In - Byte 2

DDDD

High-Impedance

Table 10-5. Write Status Register Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SUS

CMP

LB3

LB2

LB1

reserved

SRP1

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