AT25SF321 datasheet(24/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Security Register Commands

The device contains three extra pages called Security Registers that can be used for purposes such as unique device

serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are

independent of the main Flash memory.

Each page of the Security Register can be erased and programmed independently. Each page can also be

independently locked to prevent further changes.

9.1

Erase Security Registers (44h)

Before an erase Security Register Page command can be started, the Write Enable command must have been

previously issued to the device to set the WEL bit of the Status Register to a logical "1" state.

To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h must be

clocked into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register

Page to be erased must be clocked in. When the CS pin is deasserted, the device will erase the appropriate block. The

erasing of the block is internally self-timed and should take place in a time of tBE.

Since the Erase Security Register Page command erases a region of bytes, the lower order address bits do not need to

be decoded by the device. Therefore address bits A7-A0 will be ignored by the device. Despite the lower order address

bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the

CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise, the device will

abort the operation and no erase operation will be performed.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device

is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBE time to

determine if the device has finished erasing. At some point before the erase cycle completes, the RDY/BSY bit in the

Status Register will be reset back to the logical "0" state.

The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete

address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the

region to be erased is protected.

The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security registers.

Once a Lock Bit is set to 1, the corresponding Security Register will be permanently locked. The Erase Security Register

Page instruction will be ignored for Security Registers which have their Lock Bit set.

Figure 9-1. Erase Security Register Page

Table 9-1.

Security Register Addresses for Erase Security Register Page Command

Address

A23-A16

A15-A8

A7-A0

Security Register 1

00H

01H

Don’t Care

Security Register 2

00H

02H

Don’t Care

Security Register 3

00H

03H

Don’t Care

MSB

OPCODE

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