AT25SF321 datasheet(18/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase

the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the memory

array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle

state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state

if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device

is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to

determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status

Figure 7-4. Chip Erase

7.4

Program/Erase Suspend (75h)

In some code plus data storage applications, it is often necessary to process certain high-level system interrupts that

require relatively immediate reading of code or data from the Flash memory. In such an instance, it may not be possible

for the system to wait the microseconds or milliseconds required for the Flash memory to complete a program or erase

cycle. The Program/Erase Suspend command allows a program or erase operation in progress to be suspended so that

other device operations can be performed. For example, by suspending an erase operation to a particular block, the

system can perform functions such as a program or read to a different block.

Chip Erase cannot be suspended. The Program/Erase Suspend command will be ignored if it is issued during a Chip

Erase.A program operation can be performed while an erase operation is suspended, but the program operation cannot

be suspended while an erase operation is currently suspended.

Other device operations, such as a Read Status Register, can also be performed while a program or erase operation is

suspended. Table 7-4 outlines the operations that are allowed and not allowed during a program or erase suspend.

Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need to be

issued prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend command

operates independently of the state of the WEL bit in the Status Register.

To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of 75h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the program or erase operation currently in progress will be suspended within a time of

tSUSE. The Suspend (SUS) bit in the Write Status Register will be set to the logical "1" state to indicate that the program or

erase operation has been suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is

ready for another operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and

the CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no suspend operation will be

performed.

If a read operation is attempted to a suspended area (page for programming or block for erasing), then the device will

output undefined data. Therefore, when performing a Read Array operation to an unsuspended area and the device's

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