AT25SF321 datasheet(28/48 Pages) DIALOG

28 / 48 page

AT25SF321

DS-25SF321–047F–8/2017

Notes:

1. Only bits 6 through 3, 1, and 0 of the Status Register can be modified when using the Write Status Register command

2. R/W = Readable and writable

R = Readable only.

Figure 10-2. Read Status Register Byte 2

10.1.1 SRP1, SRP0 Bits

The SRP1 and SRP0 bits control whether the Status Register can be modified. The state of the WP pin along with the

values of the SRP1 and SRP0 determine if the device is software protected, hardware protected, or permanently

protected (see Table 10-3).

10.1.2 CMP, SEC, TB, BP2, BP1, BP0 Bits

The CMP, SEC, TB, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and program

operations (see Tables 8-1 and 8-2).

Quad Enable

R/W

HOLD and WP function normally (default)

HOLD and WP are I/O pins

SRP1

Status Register Protect bit-1

R/W

See table on Status Register Protection

Table 10-2. Status Register Format – Byte 2

Bit(1)

Name

Type(2)

Description

SCK

MSB

0101

41011

8122122

1720

1516

131423242829

2530

MSB

DDDDDD

MSB

DDDDDD

D DD

D D D

BYTE 2

GH-

MPEDANCE

BYTE 2

Table 10-3. Status Register Protection Table

SRP1

SRP0

Status Register

Description

Software Protected

The Status Register can be written to after a Write Enable

instruction, WEL=1.(Factory Default)

Hardware Protected

=0, the Status Register is locked and cannot be written.

Hardware

Unprotected

=1, the Status Register is unlocked and can be written to

after a Write Enable instruction, WEL=1.

Power Supply Lock-

Down (1)

When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to the (0, 0) state.

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