AT25SF321 datasheet(14/48 Pages) DIALOG

14 / 48 page

AT25SF321

DS-25SF321–047F–8/2017

Figure 6-7. Quad-I/O Read Array (Initial command or previous M5, M4

≠ 1,0)

6.5.1

Quad-I/O Read Array (EBh) with Continuous Read Mode

The Fast Read Quad I/O command can further reduce instruction overhead through setting the Continuous Read Mode

bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-6. The upper nibble (M7-4) of the Continuous Read

Mode bits controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte

instruction code. The lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins

should be high-impedance prior to the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 =

(1,0), then the next Quad-I/O Read Array command (after CS is raised and then lowered) does not require the EBh

instruction code, as shown in Fig 6-8. This reduces the command sequence by eight clocks and allows the Read address

to be immediately entered after CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the

next command (after CS is raised and then lowered) requires the first byte instruction code, thus returning to normal

operation. A Continuous Read Mode Reset command can also be used to reset (M7-0) before issuing normal

commands.

Figure 6-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5-4 =1,0)

6.6

Continuous Read Mode Reset (FFh or FFFFh)

The Continuous Read Mode bits are used in conjunction with the Dual I/O Read Array and the Quad I/O Read Array

commands to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus

allowing more efficient XIP (execute in place) with this device family.

I/O0

(SI)

SCK

I/O1

(SO)

MSB

11101011

410 11

819

17 18

Opcode

A20 A16 A12 A8

A23-A16 A15-A8

A21 A17 A13 A9

21 22

Byte 1

Byte 2

I/O2

(WP)

A22 A18 A14 A10

D2 D6

I/O3

(HOLD)

A23 A19 A15 A11

D3 D7

14 15

A4 A0 M4 M0

A7-A0

M7-M0

A6 A2 M6 M2

A7 A3 M7 M3

A5 A1 M5 M1

Dummy