ST25R3911B datasheet(72/116 Pages) STMICROELECTRONICS

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1.3.23

Mask error and wake-up interrupt register

Address: 16h

Type: RW

Table 49. Mask error and wake-up interrupt register

Bit

Name

Default

Function

Comments(1)

M_crc

1: Mask IRQ due to CRC error

M_par

1: Mask IRQ due to parity error

M_err2

1: Mask IRQ due to soft framing error

M_err1

1: Mask IRQ due to hard framing error

M_wt

1: Mask IRQ due to wake-up timer interrupt

M_wam

1: Mask Wake-up IRQ due to amplitude measurement

M_wph

1: Mask Wake-up IRQ due to phase measurement.

M_wcap

1: Mask Wake-up IRQ due to capacitance measurement

1. Default setting takes place at power-up and after set default command.

1.3.24

Main interrupt register

Address: 17h

Type: R

Table 50. Main interrupt register

Bit Name Default

Function

Comments(1)(2)

I_osc

IRQ when oscillator frequency is stable

Set after oscillator is started by setting Operation Control

I_wl

IRQ due to FIFO water level

Set during receive, informing that FIFO is almost full and has to

be read out.

Set during transmit, informing that FIFO is almost empty and

that additional data has to be sent.

I_rxs

IRQ due to start of receive

I_rxe

IRQ due to end of receive

I_txe

IRQ due to end of transmission

I_col

IRQ due to bit collision

I_tim

IRQ due to timer or NFC event

Details in Timer and NFC Interrupt register

I_err

IRQ due to error and wake-up timer

Details in Error and Wake-Up Interrupt register

1. Default setting takes place at power-up and after set default command.

2. After the reading of main interrupt register, the content is set to 0, except for bits 1 and 0, which are set to 0 after

corresponding interrupt register is read.

ST25R3911B

Registers

DS11793 - Rev 6

page 72/116

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