ST25R3911B datasheet(17/116 Pages) STMICROELECTRONICS

17 / 116 page

The External Field Detector is automatically enabled in the low power Peer Detection mode when NFCIP-1 mode

(initiator or target) is selected in the Bit rate definition register.

Additionally it can be enabled by setting bit en_fd in the Auxiliary display register.

Collision Avoidance threshold

This threshold is used during the RF Collision Avoidance sequence that is executed by sending NFC Field ON

commands (see NFC field ON commands). It can be selected in the range from 25 to 800 mVpp.

1.2.11

Power supply system

The ST25R3911B (Figure 8) features two positive supply pins, VDD and VDD_IO.

VDD is the main power supply pin. It supplies the ST25R3911B blocks through three regulators (VSP_A, VSP_D

and VSP_RF).

VDD range from 2.4 to 5.5 V is supported.

VDD_IO is used to define supply level for digital communication pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK).

Digital communication pins interface with ST25R3911B logic through level shifters, therefore the internal supply

voltage can be either higher or lower than VDD_IO. VDD_IO range from 1.65 to 5.5 V is supported.

Figure 8. ST25R3911B power supply

Power-down

support

sup3V

50 Ω

RV<3:0>

VSP_RF

REG

BGR

and

AGC

AUTOREG

VSP_A

1 kΩ

VSP_D

AGD

reg 2Bh

reg 2Ah

VSP_A

REG

VSP_D

REG

adjust

VSP_RF

VDD

Figure 8 shows the building blocks of the ST25R3911B power supply system and the signals that control it.

The power supply system contains three regulators, a power-down support block, a block generating analog

reference voltage (AGD) and a block performing automatic power supply adjustment procedure. The three

regulators are providing supply to analog blocks (VSP_A), logic (VSP_D) and transmitter (VSP_RF). The use of

VSP_A and VSP_D regulators is mandatory at 5 V power supply to provide regulated voltage to analog and logic

blocks that only use 3.3 V devices. The use of VSP_A and VSP_D regulators at 3 V supply and VSP_RF

regulator at any supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having

good PSRR. All regulator pins also have corresponding negative supply pins that are externally connected to

ground potential (VSS). The reason for separation is in decoupling of noise induced by voltage drops on the

internal power supply lines.

Figure 2 and Figure 3 show typical ST25R3911B application schematics with all regulators used. All regulator pins

and AGD voltage are buffered with capacitors. Recommended blocking capacitor values are detailed in Table 4.

Table 4. Recommended blocking capacitor values

Pins

Recommended capacitors

AGD-VSS

1 μF, in parallel with 10 nF

ST25R3911B

Application information

DS11793 - Rev 6

page 17/116

ST25R3911B Datasheet(PDF) 17 Page - STMicroelectronics

ST25R3911B Datasheet(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL