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ST25R3911B Datasheet(PDF) 22 Page - STMicroelectronics

Part # ST25R3911B
Description  High performance HF reader / NFC initiator with 1.4 W supporting VHBR and AAT
PDF  116 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST25R3911B Datasheet(HTML) 22 Page - STMicroelectronics

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Figure 12. SPI communication: reading a single byte
SCLK rising edge
Data transferred from MCU
SCLK falling edge
Data is sampled
/SS raising
edge
indicates end
of Read mode
Two leading bits
indicate Mode
/SS
SCLK
MOSI
0
1
A5
A4
A3
A2
A1
A0
X
X
D4
D3
D2
D1
D0
D7
D6
tristate
tristate
D5
MISO
SCLK rising edge
Data moved from
Address A5-A0
SCLK falling edge
Data transferred to MCU
Loading transmitting data into FIFO
Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. Difference is
that in case of loading more bytes all bytes go to the FIFO. SPI operation mode bits 10 indicate FIFO operations.
In case of loading transmitting data into FIFO all bits <C5 – C0> are set to 0. Then a bit-stream, the data to be
sent (1 to 96 bytes), can be transferred. In case the command is terminated by putting /SS high before a packet of
8 bits (one byte) is sent, writing of that particular byte in FIFO is not performed.
Figure 13 shows how to load the Transmitting Data into the FIFO.
Figure 13. SPI communication: loading of FIFO
SCLK rising edge
Data transferred from MCU
SCLK falling edge
Data is sampled
/SS raising
edge
indicates
end of
FIFO Mode
1
0
0
0
0
0
0
0
X
X
/SS
SCLK
MOSI
10 pattern
indicates
FIFO Mode
1 to 96
bytes
Start of
paylod data
Reading received data from FIFO
Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in
case of reading more bytes they all come from the FIFO. SPI operation mode bits 10 indicate FIFO operations. In
case of reading the received data from the FIFO all bits <C5 – C0> are set to 1. On the following SCLK rising
edges the data from FIFO appears as in case of read data from addressable registers. If the command is
terminated by putting /SS high before a packet of 8 bits (one byte) is read, that particular byte is considered
unread and will be the first one read in next FIFO read operation.
ST25R3911B
Application information
DS11793 - Rev 6
page 22/116



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