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ST25R3911B Datasheet(PDF) 24 Page - STMicroelectronics |
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ST25R3911B Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 116 page  Figure 16. SPI communication: direct command chaining /SS Direct command Read, Write or FIFO Mode SPI timing Table 7. SPI timing Symbol Parameter Min Typ Max Unit Comments General timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C) TSCLK SCLK period 167 - - ns TSCLK=TSCLKL+TSCLKH, use of shorter SCLK period may lead to incorrect FIFO operation. TSCLKL SCLK low 70 - 1 - TSCLKH SCLK high 70 - - - TSSH SPI reset (/SS high) 100 - - - TNCSL /SS falling to SCLK rising 25 - - First SCLK pulse TNCSH SCLK falling to /SS rising 300 - - Last SCLK pulse TDIS Data in set-up time 10 - - - TDIH Data in hold time 10 - - - Read timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C, CLOAD ≤ 50 pF) TDOD Data out delay - 20 - ns - TDOHZ Data out to high impedance delay - 20 - - Figure 17. SPI general timing ... ... ... DATAI DATAI DATAI ... tSCLKH tNCSL tSCLKL tDIS tDIH tNCSH /SS MOSI MISO SCLK ST25R3911B Application information DS11793 - Rev 6 page 24/116 |
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