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SPC572L64F2 Datasheet(PDF) 79 Page - STMicroelectronics |
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SPC572L64F2 Datasheet(HTML) 79 Page - STMicroelectronics |
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79 / 112 page ![]() DocID027866 Rev 5 79/112 SPC572Lx Electrical characteristics 111 Figure 28. DSPI PCS strobe (PCSS) timing (master mode) 3.17.2.1.2 DSPI CMOS Master Mode – Modified Timing PCSx PCSS tPCSC tPASC Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1(1) # Symbol C Characteristic Condition Value(2) Unit Pad drive(3) Load (CL)Min Max 1tSCK CC D SCK cycle time SCK drive strength Very strong 25 pF 33.0 — ns Strong 50 pF 80.0 — Medium 50 pF 200.0 — 2tCSC CC D PCS to SCK delay SCK and PCS drive strength Very strong 25 pF (N(4) × tSYS(5))–16 —ns Strong 50 pF (N(4) × tSYS(5))–16 — Medium 50 pF (N(4) × tSYS(5))–26 — PCS medium and SCK strong PCS = 50 pF SCK = 50 pF (N(4) × tSYS(5))–38 — 3tASC CC D After SCK delay SCK and PCS drive strength Very strong PCS = 0 pF SCK = 50 pF (M(6) × tSYS(5))– 35 —ns Strong PCS = 0 pF SCK = 50 pF (M(6) × tSYS(5))– 35 — Medium PCS = 0 pF SCK = 50 pF (M(6) × tSYS(5))– 35 — PCS medium and SCK strong PCS = 0 pF SCK = 50 pF (M(6) × tSYS(5))– 35 — 4tSDC CC D SCK duty cycle(7) SCK drive strength Very strong 0pF 1/2tSCK –2 1/2tSCK +2 ns Strong 0pF 1/2tSCK –2 1/2tSCK +2 Medium 0pF 1/2tSCK –5 1/2tSCK +5 PCS strobe timing |
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