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SPC572L64F2 Datasheet(PDF) 26 Page - STMicroelectronics |
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SPC572L64F2 Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 112 page ![]() Electrical characteristics SPC572Lx 26/112 DocID027866 Rev 5 Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are provided. ILKG CC P Digital input leakage 4.5 V < VDD_HV <5.5 V 0.1*VDD_HV < VIN < 0.9*VDD_HV TJ < 150 °C —— 1 µA C4.5 V < VDD_HV <5.5 V VSS_HV < VIN < VDD_HV —— 2 ILKG_MED CC C Digital input leakage for MEDIUM pad 4.5 V < VDD_HV <5.5 V 0.1*VDD_HV < VIN < 0.9*VDD_HV —— 500 nA CIN CC D Digital input capacitance GPIO input pins — — 10 pF Ethernet input pins — — 8 1. A good approximation for the variation of the minimum value with supply is given by formula VIHAUT =0.69×VDD_HV_IO. 2. A good approximation for the variation of the maximum value with supply is given by formula VILAUT =0.49×VDD_HV_IO. 3. Sum of VILAUT and VHYSAUT is guaranteed to remain above 2.6 V in the 4.5 V < VDD_HV_IO < 5.5 V. Production test done with 2.06 V limit at cold, TJ <25 oC. 4. A good approximation of the variation of the minimum value with supply is given by formula VHYSAUT =0.11×VDD_HV_IO. 5. In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For SENT requirement refer to NOTE on page 34. 6. Only for VDD_HV_IO_JTAG and VDD_HV_IO_ETH power segment. The TTL threshold are controlled by the VSIO bit. VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 4.0 V, VSIO[VSIO_xx] = 1 in the range 4.5 V < VDD_HV_IO <5.5 V. 7. For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters. 8. Only for VDD_HV_IO_JTAG and VDD_HV_IO_ETH power segment. Table 12. I/O input DC electrical characteristics (continued) Symbol C Parameter Conditions Value Unit Min Typ Max Table 13. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter Conditions Value Unit Min Typ Max |IWPU| CC T Weak pull-up current absolute value(1) VIN = 0 V VDD_POR(2) < VDD_HV_IO <3.0 V(3)(4) 10.6 * VDD_HV – 10.6 —— µA CC T VIN >VIL =1.1 V(TTL) 4.5 V < VDD_HV_IO <5.5 V —— 130 CC P VIN = 0.69* VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V 23 — 65 CC T VIN = 0.49* VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V —— 82 RWPU CC D Weak pull-up resistance 0.49* VDD_HVIO <VIN <0.69* VDD_HV_IO 4.5 V < VDD_HV_IO <5.5 V 34 — 62 k Ω |
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