SPC572L64F2 datasheet(20/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

20/112

DocID027866 Rev 5

3.4

Electromagnetic Compatibility (EMC)

EMC measurements to IC-level IEC standards are available from STMicroelectronics on

request.

3.5

Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

3.6

Operating conditions

The following table describes the operating conditions for the device for which all

specifications in the datasheet are valid, except where explicitly noted.

The device operating conditions must not be exceeded or the functionality of the device is not

guaranteed.

4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.288 V at

maximum TJ = 125 °C

5. VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_ETH, VDD_HV_OSC, VDD_HV_FLA.

6. Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ

= 150 °C remaining time at or below 5.5 V.

7. VDD_HV_ADV is also the supply for the device temperature sensor and bandgap reference.

8. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current

condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to supply.

The diode voltage varies significantly across process and temperature, but a value of 0.3 V can be used for nominal

calculations.

9. Sum of all controller pins (including both digital and analog) must not exceed 150 mA. A VDD_HV_IO power segment is

defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

10. Solder profile per IPC/JEDEC J-STD-020D.

11. Moisture sensitivity per JEDEC test method A112.

Table 8. ESD ratings(1),(2)

Parameter

Conditions

Value

Unit

ESD for Human Body Model (HBM)(3)

All pins

2000

ESD for field induced Charged Device Model (CDM)(4)

All pins

500

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification

requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.

Maximum DC parametrics variation within 10% of maximum specification”.

3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.

4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.

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