Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

LSM6DSV16BX Datasheet(PDF) 90 Page - STMicroelectronics

Part # LSM6DSV16BX
Description  iNEMO 3-axis accelerometer and 3-axis gyroscope: inertial module for UI and bone conduction with embedded machine learning core and Qvar specification
PDF  148 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LSM6DSV16BX Datasheet(HTML) 90 Page - STMicroelectronics

Back Button LSM6DSV16BX Datasheet HTML 86Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 87Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 88Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 89Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 90Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 91Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 92Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 93Page - STMicroelectronics LSM6DSV16BX Datasheet HTML 94Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 90 / 148 page
background image
9.61
TDM_CFG0 (6Ch)
TDM configuration register 0 (R/W)
Table 162. TDM_CFG0 register
1(1)
TDM_
DELAYED_CFG
TDM_BCLK
_EDGE_SEL
TDM_
SLOT_SEL
0(2)
TDM_
WCLK_1
TDM_
WCLK_0
TDM_WCLK
_BCLK_SEL
1. This bit must be set to 1 for the correct operation of the device.
2. This bit must be set to 0 for the correct operation of the device.
Table 163. TDM_CFG0 register description
TDM_DELAYED_CFG
Enables TDM delayed configuration. Default value: 0
(0: disabled; 1: enabled)
TDM_BCLK_EDGE_SEL
BCLK edge selection for TDM interface. Default value: 0
(0: sampling on BCLK rising edge; 1: sampling on BCLK falling edge)
TDM_SLOT_SEL
Selection of TDM slot for transmission. Default value: 0
(0: slot {0, 1, 2} is selected; 1: slot {4, 5, 6} is selected)
TDM_WCLK_[1:0]
TDM word clock frequency selection (see Table 164)
TDM_WCLK_BCLK_SEL
Selection of cross association between WCLK and BCLK frequencies (see Table 164)
Table 164. WCLK and BCLK frequencies
TDM_WCLK_BCLK_SEL
TDM_WCLK_[1:0]
WCLK
BCLK
0
01
16 kHz
2048 kHz
1
00
8 kHz
2048 kHz
LSM6DSV16BX
TDM_CFG0 (6Ch)
DS13771 - Rev 2
page 90/148



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com