ISL68227IRAZ datasheet(11/100 Pages) RENESAS

11 / 100 page

ISL68227

1. Overview

FN9333 Rev.1.00

Page 11 of 99

Oct.1.20

1.5

Functional Pin Descriptions

See Table 5 on page 30 for design layout considerations.

Number

Pin Name

Description

1, 2, 3, 4, 5,

6, 55, 56, 57,

58, 59, 60

PWM [11:0]

Pulse-Width Modulation (PWM) outputs. Connect these pins to the PWM input pins of 3.3V

logic-compatible, smart power stages, driver ICs, or DrMOS.

CFP

Thermal warning indicator. This open-drain output is pulled low if a sensed over-temperature occurs at the

TEMP pins.

nVRHOT

Indicator of high VR temperature. This open-drain output is pulled low in the event of a sensed

over-temperature.

9, 11, 14, 16,

46, 47

DNC

Do not connect to these pins.

10, 12

GND

Connect to ground.

Input pin used for enable control of the output. Connect to ground if not used.

Open-drain, power-good indicator for the output.

VINSEN

Input voltage sense pin for the VIN supply voltage.

VMON

Input voltage sense pin for the driver supply voltage.

19, 21, 23,

25, 27, 29,

31, 33, 35,

37, 39, 41

CSRTN [11:0]

The CS and CSRTN pins are current-sense inputs to individual phase differential amplifiers. Unused

phases should have their respective current-sense inputs grounded. The CS and CSRTN pins support

smart power stage, DCR, and resistor sensing. Connection details depend on the current-sense method

chosen.

20, 22, 24,

26, 28, 30,

32, 34, 36,

38, 40, 42

CS [11:0]

RGND

Negative differential voltage sense input for the output. Connect to the negative remote sensing point.

Place a 3300pF capacitor across the pair at the pins.

VSEN

Positive differential voltage sense input for the outputs. Connect to the positive remote sensing point.

Place a 3300pF capacitor across the pair at the pins.

TEMP

Input pin for sensing external temperature measurement at the outputs. Supports NTC-based temperature

sensing and smart power stage sensing. Connect to ground if not used.

CONFIG

Configuration ID selection pin. Attach a resistor from this pin to GND.

ADDRESS

SMBus/PMBus address selection pin. Attach a resistor from this pin to GND.

VCC

Chip primary bias input. Connect this pin directly to a +3.3V supply with a 1µF or greater MLCC bypass

capacitor.

VCCS

Internally generated 1.2V LDO logic supply from VCC. Decouple with a 4.7µF or greater MLCC (X5R or

better).

nPMALERT

Open-drain output pin for alerting the SMBus host.

PMSCL

Serial clock signal pin for the SMBus interface.

PMSDA

Serial data signal pin for the SMBus interface.

EPAD

GND

The package pad serves as the GND return for all IC functions. Connect directly to the system GND plane

with multiple vias.

ISL68227IRAZ Datasheet(PDF) 11 Page - Renesas Technology Corp

ISL68227IRAZ Datasheet(HTML) 11 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL