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UPSD3422 Datasheet(PDF) 69 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 300 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 MCU clock generation 69/300 14.2.2 USB_CLK The UPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to generate the 48MHz USB_CLK clock on a wide range of fOSC frequencies. The USB_CLK must be at 48MHz for the USB to function properly. The PLL is enabled after power up. The power on lock time for the PLL clock is about 200µs, and the firmware should wait that much time before enabling the USB_CLK by setting the UPLLCE Bit in the CCON0 register to '1.' The PLL is disabled in Power-down mode, it can also be disabled or enabled by writing to the PLLEN Bit in the CCON0 register. The PLL output clock frequency (fUSB_CLK) can be determined by using the following formula: where PLLM and PLLD are the multiplier and divisor that are specified in the CCON1 register. The fOSC, the PLLM and PLLD range must meet the following conditions to generate a stable USB_CLK: a) –1 ≤PLLM ≤30 (binary: [11111] ≤PLLM[4:0] ≤[11110]), b) –1 ≤PLLD ≤14 (binary: [1111] ≤PLLD[3:0] ≤[1110]), and c) fOSC/(PLLD+2) must be equal to or greater than 3MHz. The USB requires a 48MHz clock to operate correctly. The PLLM[4:0] and PLLD[3:0] values must be selected so as to generate a USB_CLK that is as close to 48MHz as possible at different oscillator frequencies (fOSC). Table 26 lists some of the PLLM and PLLD values that can be used on common fOSC frequencies. Table 26. PLLM and PLLD values for different fOSC frequencies fOSC (MHz) PLLM[4:0] PLLD[3:0] fUSB_CLK (MHz) decimal binary decimal binary 40.0 22 10110 8 1000 48.0 36.0 6 00110 1 0001 48.0 33.0 30 11110 9 1001 48.0 30.0 14 01110 3 0011 48.0 24.0 18 10010 3 0011 48.0 16.0 28 11100 3 0011 48.0 12.0 30 11110 2 0010 48.0 8.0 22 10110 0 0000 48.0 6.0 30 11110 0 0000 48.0 3.0 30 11110 –1 1111 48.0 f USBCLK f OSC PLLM 2 + () × [] PLLD 2 + () 2 × [] ⁄ = Obsolete Product(s) - Obsolete Product(s) |
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