UPSD3422_V01 datasheet(26/300 Pages) STMICROELECTRONICS

26 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

Pin descriptions

UPSD3422, UPSD3433, UPSD3434, UPSD3454

26/300

ALE

N/A

Address Latch

signal, external bus

RESET_IN

Active low reset

input

XTAL1

Oscillator input pin

for system clock

XTAL2

Oscillator output pin

for system clock

DEBUG

I/O

I/O to the MCU

debug unit

PA0

N/A

I/O

General I/O port pin

All Port A pins

support:

– PLD Macrocell

outputs, or

– PLD inputs, or

– Latched address

out (A0-A7), or

– Peripheral I/O

mode

PA1

N/A

I/O

General I/O port pin

PA2

N/A

I/O

General I/O port pin

PA3

N/A

I/O

General I/O port pin

PA4

N/A

I/O

General I/O port pin

PA5

N/A

I/O

General I/O port pin

PA6

N/A

I/O

General I/O port pin

PA7

N/A

I/O

General I/O port pin

PB0

I/O

General I/O port pin

All Port B pins

support:

– PLD Macrocell

outputs, or

– PLD inputs, or

– Latched address

out (A0-A7 or

A8-A15)

PB1

I/O

General I/O port pin

PB2

I/O

General I/O port pin

PB3

I/O

General I/O port pin

PB4

I/O

General I/O port pin

PB5

I/O

General I/O port pin

PB6

I/O

General I/O port pin

PB7

I/O

General I/O port pin

JTAGTMS

TMS

JTAG pin (TMS)

JTAGTCK

TCK

JTAG pin (TCK)

PC2

I/O

General I/O port pin

PLD Macrocell

output, or PLD input

PC3

TSTAT

N/A

I/O

General I/O port pin

Optional JTAG

Status (TSTAT)

PLD, Macrocell

output, or PLD input

PC4

TERR

N/A

I/O

General I/O port pin

Optional JTAG

Status (TERR)

PLD, Macrocell

output, or PLD input

JTAGTDI

TDI

JTAG pin (TDI)

JTAGTDO

TDO

JTAG pin (TDO)

Table 2.

Pin definitions (continued)

Port pin

Signal

name

80-pin

No.

52-pin

No.(1)

In/out

Function

Basic

Alternate 1

Alternate 2

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422 Datasheet(PDF) 26 Page - STMicroelectronics

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