UPSD3422_V01 datasheet(94/300 Pages) STMICROELECTRONICS

94 / 300 page

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Supervisory functions

UPSD3422, UPSD3433, UPSD3434, UPSD3454

94/300

In this example,

tMACH_CYC = 100ns (4 MCU_CLK periods x 25ns)

NOVERFLOW = 2

24 = 16777216 up-counts

WDTPERIOD = 100ns X 16777216 = 1.67 seconds

The actual value will be slightly longer due to PFQ/BC.

19.5.1

Firmware example

The following 8051 assembly code illustrates how to operate the WDT. A simple statement

in the reset initialization firmware enables the WDT, and then a periodic write to clear the

WDT in the main firmware is required to keep the WDT from overflowing. This firmware is

based on the example above (40MHz fOSC, CCON0 = 10h, BUSCON = C1h).

For example, in the reset initialization firmware (the function that executes after a jump to

the reset vector):

Somewhere in the flow of the main program, this statement will execute periodically to reset

the WDT before its time-out period of 1.67 seconds. For example:

MOV AE, #AA

; enable WDT by writing value to

; WDKEY other than 55h

MOV A6, #00

; reset WDT, loading 000000h.

; Counting will automatically

; resume as long as 55h in not in

; WDKEY

Table 52.

WDKEY: Watchdog timer key register (SFR AEh, reset value 55h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDKEY[7:0]

Table 53.

WDKEY register bit definition

Bit

Symbol

R/W

Definition

[7:0]

WDKEY

55h disables the WDT from counting. 55h is automatically

loaded in this SFR after any reset condition, leaving the WDT

disabled by default.

Any value other than 55h written to this SFR will enable the

WDT, and counting begins.

Table 54.

WDRST: Watchdog timer reset counter register (SFR A6h, reset value

00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDRST[7:0]

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