UPSD3422_V01 datasheet(97/300 Pages) STMICROELECTRONICS

97 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

Standard 8032 timer/counters

97/300

period (12 / fOSC, seconds). However, if MCU_CLK is divided by the SFR CCON0, then the

sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In

this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than

one MCU machine cycle, tMACH_CYC. Section 19.5: Watchdog timer, WDT on page 92

explains how to estimate tMACH_CYC.

20.3

SFR, TCON

Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides

information about them. See Table 56 on page 97.

Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware

when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For

system information on all of these interrupts, see Table 17 on page 63, Interrupt Summary.

Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not

the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered.

Table 56.

TCON: Timer control register (SFR 88h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Table 57.

TCON register bit definition

Bit

Symbol

R/W

Definition

7TF1

Timer 1 overflow interrupt flag. Set by hardware upon overflow.

Automatically cleared by hardware after firmware services the

interrupt for Timer 1.

TR1

R,W

Timer 1 run control. 1 = Timer/Counter 1 is on, 0 =

Timer/Counter 1 is off.

5TF0

Timer 0 overflow interrupt flag. Set by hardware upon overflow.

Automatically cleared by hardware after firmware services the

interrupt for Timer 0.

TR0

R,W

Timer 0 run control. 1 = Timer/Counter 0 is on, 0 =

Timer/Counter 0 is off.

3IE1

Interrupt flag for external interrupt pin, EXTINT1. Set by

hardware when edge is detected on pin. Automatically cleared

by hardware after firmware services EXTINT1 interrupt.

2IT1

R,W

Trigger type for external interrupt pin EXTINT1. 1 = falling

edge, 0 = low-level

1IE0

Interrupt flag for external interrupt pin, EXTINT0. Set by

hardware when edge is detected on pin. Automatically cleared

by hardware after firmware services EXTINT0 interrupt.

0IT0

R,W

Trigger type for external interrupt pin EXTINT0. 1 = falling

edge, 0 = low-level

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