IMX8MPCEC datasheet(43/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

3.6.1

Differential I/O output buffer impedance

The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA

STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface

Circuits (2001) for details.

3.6.2

DDR I/O output buffer impedance

Table 32 shows DDR I/O output buffer impedance of i.MX 8M Plus family of processors.

3.7

System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 8M Plus processor.

Table 32. DDR I/O output buffer impedance

Parameter

Symbol

Test Conditions DSE

(Drive Strength)

Typical

Note

Unit

NVCC_DRAM = 1.2

V (DDR4)

NVCC_DRAM = 1.1

V (LPDDR4)

Output Driver

Impedance1, 2, 3

1 Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2 Calibration is done against 240

 external reference resistor.

3 Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

Rdrv

000000

Hi-Z

—



000001

480

—

000010

240

—

000011

160

—

001000

120

—

001001

—

001010

—

001011

—

011000

4 Output driver impedance values are included in the IBIS model.

011001

011010

—

011011

—

111000

111001

—

111010

111011

—

111110

—

111111

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